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參數(shù)資料
| 型號： | BS62LV2006STI55 |
| 廠商： | BRILLIANCE SEMICONDUCTOR, INC. |
| 英文描述： | Very Low Power CMOS SRAM 256K X 8 bit |
| 中文描述： | 非常低功耗CMOS SRAM 256K × 8位 |
| 文件頁數(shù)： | 3/11頁 |
| 文件大?。?/td> | 361K |
| 代理商： | BS62LV2006STI55 |
BS62LV2006
R0201-BS62LV2006
Revision
May.
1.3
2006
3
n
DC ELECTRICAL CHARACTERISTICS (T
A
= -40
O
C to +85
O
C)
PARAMETER
NAME
PARAMETER
TEST CONDITIONS
MIN.
TYP.
(1)
MAX.
UNITS
V
CC
Power Supply
2.4
--
5.5
V
V
IL
Input Low Voltage
-0.5
(2)
--
0.8
V
V
IH
Input High Voltage
2.2
--
V
CC
+0.3
(3)
V
I
IL
Input Leakage Current
V
CC
= Max, V
IN
= 0V to V
CC
--
--
1
UA
I
LO
Output Leakage Current
V
CC
= Max, CE1= V
IH
, CE2= V
IL
, or
OE = V
IH
, V
I/O
= 0V to V
CC
--
--
1
UA
V
OL
Output Low Voltage
V
CC
= Max, I
OL
= 2.0mA
--
--
0.4
V
V
OH
Output High Voltage
V
CC
= Min, I
OH
= -1.0mA
2.4
--
--
V
V
CC
=3.0V
--
--
--
--
--
--
--
--
--
--
--
--
--
--
0.1
0.6
23
55
2
10
0.5
1.0
2.0
20
I
CC
(5)
Operating Power Supply
Current
CE1 = V
IL
, CE2 = V
IH
,
I
DQ
= 0mA, f = F
MAX
(4)
V
CC
=5.0V
mA
V
CC
=3.0V
I
CC1
Operating Power Supply
Current
CE1 = V
IL
, CE2 = V
IH
,
I
DQ
= 0mA, f = 1MHz
V
CC
=5.0V
mA
V
CC
=3.0V
I
CCSB
Standby Current
–
TTL
CE1 = V
IH
, or CE2 = V
IL
,
I
DQ
= 0mA
V
CC
=5.0V
mA
V
CC
=3.0V
I
CCSB1
(6)
Standby Current
–
CMOS
CE1
≧
V
CC
-0.2V or CE2
≦
0.2V,
V
IN
≧
V
CC
-0.2V or V
IN
≦
0.2V
V
CC
=5.0V
uA
1. Typical characteristics are at T
=25
O
C and not 100% tested.
2. Undershoot: -1.0V in case of pulse width less than 20 ns.
3. Overshoot: V
CC
+1.0V in case of pulse width less than 20 ns.
4. F
MAX
=1/t
5. I
CC (MAX.)
is 22mA/53mA at V
=3.0V/5.0V and T
=70
O
C.
6. I
CCSB1(MAX.)
is 0.7uA/6.0uA at V
CC
=3.0V/5.0V and T
A
=70
O
C.
n
DATA RETENTION CHARACTERISTICS (T
A
= -40
O
C to +85
O
C)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
TYP.
(1)
MAX.
UNITS
V
DR
V
CC
for Data Retention
CE1
≧
V
CC
-0.2V or CE2
≦
0.2V,
V
IN
≧
V
CC
-0.2V or V
IN
≦
0.2V
1.5
--
--
V
I
CCDR
(3)
Data Retention Current
CE1
≧
V
CC
-0.2V or CE2
≦
0.2V,
V
IN
≧
V
CC
-0.2V or V
IN
≦
0.2V
--
0.05
1.0
uA
t
CDR
Chip Deselect to Data
Retention Time
0
--
--
ns
t
R
Operation Recovery Time
See Retention Waveform
t
RC
(2)
--
--
ns
1. V
CC
=1.5V, T
=25
O
C and not 100% tested.
2. t
RC
= Read Cycle Time.
3. I
CCRD(Max.)
is 0.5uA at T
A
=70
O
C.
n
LOW V
CC
DATA RETENTION WAVEFORM (1) (CE1 Controlled)
CE1
Data Retention Mode
V
DR
≧
1.5V
V
CC
t
CDR
V
CC
t
R
V
IH
V
IH
CE1
≧
V
CC
- 0.2V
V
CC
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| BS62LV2006STI70 | Very Low Power CMOS SRAM 256K X 8 bit |
| BS62LV2006TC55 | Very Low Power CMOS SRAM 256K X 8 bit |
| BS62LV2006TC70 | Very Low Power CMOS SRAM 256K X 8 bit |
| BS62LV2006TI55 | Very Low Power CMOS SRAM 256K X 8 bit |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| BS62LV2006STI-55 | 制造商:BSI 制造商全稱:Brilliance Semiconductor 功能描述:Very Low Power/Voltage CMOS SRAM 256K X 8 bit |
| BS62LV2006STI70 | 制造商:BSI 制造商全稱:Brilliance Semiconductor 功能描述:Very Low Power CMOS SRAM 256K X 8 bit |
| BS62LV2006STI-70 | 制造商:BSI 制造商全稱:Brilliance Semiconductor 功能描述:Very Low Power/Voltage CMOS SRAM 256K X 8 bit |
| BS62LV2006STIG55 | 制造商:BSI 制造商全稱:Brilliance Semiconductor 功能描述:Very Low Power/Voltage CMOS SRAM 256K X 8 bit |
| BS62LV2006STIG70 | 制造商:BSI 制造商全稱:Brilliance Semiconductor 功能描述:Very Low Power CMOS SRAM 256K X 8 bit |
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