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參數(shù)資料
| 型號(hào)： | BD9007HFP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 2 A SWITCHING REGULATOR, 505 kHz SWITCHING FREQ-MAX, PSSO7 |
| 封裝： | ROHS COMPLIANT, HRP-7 |
| 文件頁數(shù)： | 5/18頁 |
| 文件大?。?/td> | 484K |
| 代理商： | BD9007HFP |
BD9006F, BD9006HFP, BD9007F, BD9007HFP
Technical Note
13/17
www.rohm.com
2009.05 - Rev.A
2009 ROHM Co., Ltd. All rights reserved.
fr =
[Hz]
fr =
[Hz]: Resonance
fESR =
[Hz]: Phase lead
A -90 phase-delay occurs.
2． For output capacitors having high ESR, such as electrolyte capacitor
For output capacitors that have high ESR (i.e., several ), the phase compensation setting procedure becomes
comparatively simple. Since the DC/DC converter application has a LC resonant circuit attached to the output, a -180
phase-delay occurs in that area. If ESR component is present, however a +90 phase-lead occurs to shift the phase
delay to -90. Since the phase delay should be set within 150, it is a very effective method but tends to increase the
ripple component of the output voltage.
(1) LC resonant circuit
(2) With ESR provided
According to changes in phase characteristics, due to the ESR, only one phase lead should be inserted.
For this phase lead, select either of the methods shows below:
(3) Insert Feedback Resistance in the C.
(4) Insert the R3 in integrator.
To cancel the LC resonance, the frequency to insert the phase lead should be set close to the LC resonant frequency.
The setting above have is estimated. Consequently, the setting may be adjusted on the actual system. Furthermore, since
these characteristics vary with the layout of PCB loading conditions, precise calculations should be made on the actual system.
3．For output capacitors having low ESR, such as low impedance electrolyte capacitor or OS-CON
In order to use capacitors with low ESR (i.e., several tens of m), two phase-leads should be inserted so that a -180phase-
delay, due to LC resonance, will be compensated. The following section shows a typical phase compensation procedure.
(1) Phase compensation with secondary phase lead
To set phase lead frequency, insert both of the phase leads close to the LC resonant frequency. According to empirical
rule, setting the phase lead frequency fZ2 with R3 and C2 lower than the LC resonant frequency fr, and the phase lead
frequency fZ1 with the R1 and C1 higher than the LC resonant frequency fr, will provide stable application conditions.
Vcc
Vo
L
C
＋
INV
R2
A
FB
Vo
C2
C1
R1
R2
A
Vo
C2
R1
R3
INV
FB
1
2πC2R3
1
2πC1R1
Phase lead fz =
[Hz]
Phase lead fz =
[Hz]
At this resonance point, a-180
phase-delay occurs.
1
2π√LC
1
2π√LC
1
2πRESRC
Vcc
Vo
L
C
RESR
INV
R2
A
FB
Vo
C2
R1
R3
C1
Phase lead：
fz1 =
[Hz]
1
2πR1C1
Phase lead：
fz2 =
[Hz]
1
2πR3C2
LC resonant：
fr =
[Hz]
frequency
1
2π√LC
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