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參數(shù)資料
| 型號： | BD9007HFP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 2 A SWITCHING REGULATOR, 505 kHz SWITCHING FREQ-MAX, PSSO7 |
| 封裝： | ROHS COMPLIANT, HRP-7 |
| 文件頁數(shù)： | 3/18頁 |
| 文件大?。?/td> | 484K |
| 代理商： | BD9007HFP |
BD9006F, BD9006HFP, BD9007F, BD9007HFP
Technical Note
11/17
www.rohm.com
2009.05 - Rev.A
2009 ROHM Co., Ltd. All rights reserved.
Fig.24
Design Method
Sample Calculations
4. Selection of diode (D1)
Set diode rating with an adequate margin to the
maximum load current. Also, make setting of the rated
inverse voltage with an adequate margin to the
maximum input voltage.
A diode with a low forward voltage and short reverse
recovery time will provide high efficiency.
When VIN(max.)=35V
Io=(max.)2A
Diode ratings must include:
Current over 2A
Withstand minimum 35V
5. Selection of input capacitor (CIN, C28)
Two capacitors, ceramic capacitor CIN and bypass
capacitor C28 should be inserted between the VIN and
GND. Be sure to insert a ceramic capacitor of 2 to 10F
for the CIN. The capacitor C28 should have a low ESR
and a significantly large ripple current. The ripple
current IRMS can be obtained by the following formula:
Select capacitors that can accept this ripple current.
If the capacitance of CIN and C28 is not optimum, the IC
may malfunction.
Vo×(VIN-Vo)/VIN
2
When VIN=13.2V, Vo=3.3V and Io=1A:
IRMS=0.433A
3.3×(13.2-3.3)/(13.2)
2
6. Setting of oscillating frequenPcy
Referring Fig.24 on the following page, select R for the
oscillating frequency to be used.
When f=300kHz
From p.11 Fig.24, a resistance of RT=51k is selected.
RT=51k
7. Setting of phase compensation (R3 and C1)
The phase margin can be set through inserting a capacitor
or a capacitor and resistor between the INV pin and the
FB pin. Each set value varies with the output coil,
capacitance, I/O voltage, and load. Therefore, set the
phase compensation to the optimum value according to
these conditions. (For details, refer to Application circuit on
page.11～)
If this setting is not optimum, output oscillation may
result.
※
Please contact us if there are any questions regarding phase
compensation configuration.
※
The set values listed above are all reference values. On the actual mounting of the IC, the characteristics may vary with the routing of wirings
and the types of parts in use. In the connection, it is recommended to thoroughly verify these values on the actual system prior to use.
●
Directions for pattern layout of PCB
①
Arrange the wirings shown by heavy lines as short as possible in
a broad pattern.
②
Locate the input ceramic capacitor CIN as close to the VIN-GND
pin as possible.
③
Locate the RT as close to the GND pin as possible.
④
Locate the R1 and R2 as close to the INV pin as possible, and
provide the shortest wiring from the R1 and R2 to the INV pin.
⑤
Locate the R1 and R2 as far away from the L1 as possible.
⑥
Separate POWER GND (Schottky diode, I/O capacitor’s GND)
and SIGNAL GND (RT, GND), so that SW noise doesn’t have an
effect on SIGNAL GND at all.
⑦
Design the POWER wire line as wide and short as possible.
⑧
Additional pattern for C2 and C3 expand compensation flexibility.
RT
IN
V
SW
BD9006HFP
GND
V
IN
EN
FB
C28
POWER
GND
R1
R2
C2
L1
SIGNAL GND
GND
L
O
A
D
CIN
C1
C3
R3
RT
D1
①
②
⑥
⑤
④
⑧
③
IRMS=1×
√
IRMS=Io×
√
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