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參數(shù)資料
| 型號： | BD616LV4017DIG70 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | DRAM |
| 英文描述： | Very Low Power/Voltage CMOS SRAM 256K X 16 bit |
| 中文描述： | 非常低功率/電壓CMOS SRAM的256 × 16位 |
| 文件頁數(shù)： | 8/10頁 |
| 文件大?。?/td> | 265K |
| 代理商： | BD616LV4017DIG70 |
Revision 2.1
Jan. 2004
8
R0201-BS616LV4017
WRITE CYCLE2
(1,6)
BSI
BS616LV4017
t
WC
t
CW
(10)
(2)
t
WP
t
AW
t
WHZ
(4,11)
t
AS
t
WR
(3)
t
DH
t
DW
D
IN
D
OUT
WE
CE
ADDRESS
(5)
t
OW
(7)
(8)
(8,9)
t
BW
LB,UB
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals
must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of
the signal that terminates the write.
3. T
WR
is measured from the earlier of CE or WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase
to the outputs must not be applied.
5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE
transition, output remain in a high impedance state.
6. OE is continuously low (OE = V
IL
).
7. D
OUT
is the same phase of write data of this write cycle.
8. D
OUT
is the read data of next address.
9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of
opposite phase to the outputs must not be applied to them.
10. T
CW
is measured from the later of CE going low to the end of write.
11. The parameter is guaranteed but not 100% tested.
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