Note (1): The 8 bits of the NVR register (7:0) are mapped to the listed bits of the target in order. Unused bits are always at the MSb (bit 7) " />
參數(shù)資料
型號： BBT3821LP-JH
廠商： Intersil
文件頁數(shù)： 48/75頁
文件大小： 0K
描述： IC RE-TIMER OCTAL 192-BGA
標(biāo)準(zhǔn)包裝： 90
類型： 時鐘和數(shù)據(jù)恢復(fù)（CDR），多路復(fù)用器
PLL： 無
輸入： CML
輸出： CML，CMOS
電路數(shù)： 1
比率 - 輸入:輸出： 8:8
差分 - 輸入:輸出： 是/是
頻率 - 最大： 1.59Gbps
電源電壓： 1.3 V ~ 2.5 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 192-EBGA
供應(yīng)商設(shè)備封裝： 192-EBGA-B（17x17）
包裝： 托盤
52
Note (1): The 8 bits of the NVR register (7:0) are mapped to the listed bits of the target in order. Unused bits are always at the MSb (bit 7) end.
Note (2): The target register pair are overlapped, ignoring the ‘reserved’ bits in one where used bits occur in the same location in the other. Thus the mapping from the
NVR register is: 1.C001.[15:12], 3.C001.11, 1.C001.[10:8].
Note (3): The mapping from the NVR register is: 1.C004.[11:8], 3.C004.[3:0]
S + 7
1.36865.[7:0]
1.9001.[7:0]
LASI TX Alarm Control
S + 8
1.36865.[10:8]
& 1.36866.[3:0]
1.9001.[10:8],
1.9002.[3:0]
LASI TX Alarm & LASI Control
S + 9
1.36870.
1.9006
DOM TX flag control
S + 10
S + A
1.36871.
1.9007
DOM RX flag control
S + 11
S + B
1.49170.[1:0],
1.49168.[5:0]
1.C012.[1:0],
1.C010.[5:0]
GPIO LASI & Pin Direction Configuration
S + 12
S + C
1.49170.[11:8,5:2],
1.C012.[11:8,5:2]
GPIO LASI control
S + 13
S + D
1.49170.[13:12],
1.49171.[5:0]
1.C012.[13:12],
1.C013.[5:0]
TX_FAULT polarity, GPIO LASI & Output Control Table 49 &
S + 14
S + E
1.49176
1.C018
DOM Control
S + 15
S + F
1.49177.[7:0]
1.C019.[7:0]
Indirect DOM Mem Address Lane2
S + 16
S + 10
1.49177.[15:8]
1.C019.[15:8]
Indirect DOM Mem Address Lane3
S + 17
S + 11
1.49178.[7:0]
1.C01A.[7:0]
Indirect DOM Mem Address Lane0
S + 18
S + 12
1.49178.[15:8]
1.C01A.[15:8]
Indirect DOM Mem Address Lane1
S + 19
S + 13
1.49179.[7:0]
1.C01B.[7:0]
Indirect DOM Dev Address Lane2
S + 20
S + 14
1.49179.[15:8]
1.C01B.[15:8]
Indirect DOM Dev Address Lane3
S + 21
S + 15
1.49180.[7:0]
1.C01C.[7:0]
Indirect DOM Dev Address Lane0
S + 22
S + 16
1.49180.[15:8]
1.C01C.[15:8]
Indirect DOM Dev Address Lane1
S + 23
S + 17
1.49181.[7:0]
1.C01D.[7:0]
Optical I/F Pin Polarity Control
S + 24
S + 18
4.49152.[7:0]
4.C000.[7:0]
PHY XS control 2
S + 25
S + 19
4.49152.[15:8]
4.C000.[15:8]
PHY XS control 2
S + 26
S + 1A
4.49153.[7:0]
4.C001.[7:0]
PHY XS control 3
S + 27
S + 1B
4.49153.[15:8]
4.C001.[15:8]
PHY XS control 3
S + 28
S + 1C
4.49154.[7:0]
4.C002.[7:0]
PHY XS Error Code
S + 29
S + 1D
4.49155.[7:0]
4.C003.[7:0]
PHY XS IDLE Code
S + 30
S + 1E
4.49156.[11:8,3:0]
4.C004.[11:8,3:0]
PHY XS Loopback Control
S + 31
S + 1F
3.49152.[7:0]
3.C000.[7:0]
PCS control 2
S + 32
S + 20
3.49152.[15:8]
3.C000.[15:8]
PCS control 2
S + 33
S + 21
3.49153.[7:0]
3.C001.[7:0]
PCS control 3
S + 34
S + 22
1:3.49153.[15:8]
1:3.C001.[15:8]
PCS control 3/PMA control 2
S + 35
S + 23
3.49154.[7:0]
3.C002.[7:0]
PCS Error Code
S + 36
S + 24
3.49155.[7:0]
3.C003.[7:0]
PCS IDLE Code
S + 37
S + 25
1.49156.[11:8]
3.49156.[3:0]
1.C004.[11:8]
3.C004.[3:0]
PCS/PMA Loopback Control
S + 38
S + 26
1.49163.[9:2]
1.C00B.[9:2]
Miscellaneous Adjustments
S + 39
S + 27
4.49163.[9:2]
4.C00B.[9:2]
BitBlitz Internal Test Control
Table 92. AUTO-CONFIGURE REGISTERS (Continued)
Auto-configure Pointer is (S), Auto-configure Size is (N), from 1.8106’h & 1.8105’h respectively
NVR ADDRESS
TARGET REGISTER BITS ADDRESS (1)
TARGET NAME(1)
DETAILS
DEC
HEX
DEC
HEX
BBT3821
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