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參數(shù)資料
| 型號： | BBT3821LP-JH |
| 廠商： | Intersil |
| 文件頁數(shù)： | 37/75頁 |
| 文件大小： | 0K |
| 描述： | IC RE-TIMER OCTAL 192-BGA |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 類型： | 時(shí)鐘和數(shù)據(jù)恢復(fù)（CDR），多路復(fù)用器 |
| PLL： | 無 |
| 輸入： | CML |
| 輸出： | CML，CMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 8:8 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 1.59Gbps |
| 電源電壓： | 1.3 V ~ 2.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 192-EBGA |
| 供應(yīng)商設(shè)備封裝： | 192-EBGA-B（17x17） |
| 包裝： | 托盤 |
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42
Note (1): These values may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details).
Note (2): PCS loopback via bit 3.0.14 (Table 57) is NOT permitted by IEEE 802.3ae-2002 for 10GBASE-X PCS devices. Many XENPAK hosts, however, expect this
loopback (which is mandatory for 10GBASE-R PCS devices). Setting this bit will enable this loopback, but cause the BBT3821 to be non-conforming to the
current 802.3 specification. See “Loopback Modes ” on page 13).
Note (3): These bits are overridden by PCS XAUI_EN, see also Table 65.
Note (4): This state machine is implemented according to IEEE 802.3ae-2002 clause 48.2.6.
Note (1): “D” is either 3 for PCS or 4 for PHY XS. Behavior of the two devices is entirely independent of each other.
Note (1): The value may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details).
Note (1): The value may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details).
3.49153.6
PCS AKR_SM_EN
1 = enable random
A/K/R
0 = /K/ only(3)
0’b(1)
R/W
Enable pseudo- random A/K/R(4) in Inter Packet Gap
(IPG) on PCS transmitter side (vs. /K/ only)
3.49153.5
PCS TRANS_EN
1 = enable
0 = disable(3)
Overridden by
XAUI_EN, see
0’b(1)
R/W
This bit enables the transceiver to translate an “IDLE”
pattern in the internal FIFOs (matching the value of
register 3.C003’h) to and from the XAUI IDLE /K/
comma character or /A/, /K/ & /R/ characters.
3.49153.4
Reserved
3.49153.3
TX_SDR
PCS receive
data rate
0’b(1)
R/W
1 = PCS egress takes data from PHY XS at half speed
0 = PCS egress takes data from PHY XS at full speed
3.49153.2:0
Reserved
001’b
Table 64. PCS CONTROL REGISTER 3 (Continued)
MDIO REGISTER ADDRESS = 3.49153 (3.C001’h)
BIT
NAME
SETTING
DEFAULT
R/W
DESCRIPTION
Table 65. PCS or PHY XS XAUI_EN CONTROL OVERRIDE FUNCTIONS
BITS OVERRIDDEN BY XAUI_EN Bit, D.49153.11 (D.C001’h.11) = 1’b (1)
REG. BIT(1)
NAME
OVERRIDE TO
DEFAULT
R/W
DESCRIPTION
D.49153.5
TRANS_EN
1 = enable
0’b
R/W
Translates /A/K/R/ to-from /I/
D.49153.6
AKR_SM_EN
1 = enable
0’b
R/W
Generate pseudo-random /A/K/R/
D.49152.1
A_ALIGN_DIS
0 = enabled
1’b
R/W
Aligns data on incoming “||A||”
D.49152.4
PCS_SYNC_EN
1 = enable
0’b
R/W
IEEE Clause 48.2.6 State Machine
D.49152.7
DSKW_SM_EN
1 = enable
0’b
R/W
IEEE Clause 48.2.6 State Machine
D.49154
ERROR Code
FE’h
R/W
Internal FIFO ERROR character
Table 66. PCS INTERNAL ERROR CODE REGISTER
MDIO REGISTER, ADDRESS = 3.49154 (3.C002’h)
BIT
NAME
SETTING
DEFAULT(1)
R/W
DESCRIPTION
3.49154.15:8
Reserved
3.49154.7:0
PCS ERROR
Desired Value(2)
FE’h
R/W
Error Code. These bits allow the internal FIFO
ERROR control character to be programmed.
Table 67. PCS INTERNAL IDLE CODE REGISTER
MDIO REGISTER ADDRESS = 3.49155 (3.C003’h)
BIT
NAME
SETTING
DEFAULT(1)
R/W
DESCRIPTION
3.49155.15:8
Reserved
3.49155.7:0
PCS XG_IDLE
Desired Value
07’h
R/W
IDLE pattern in internal FIFOs for translation
to/from XAUI IDLEs
BBT3821
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