Note (1): The values may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for d" />
參數(shù)資料
型號： BBT3821LP-JH
廠商： Intersil
文件頁數(shù)： 31/75頁
文件大?。?/td> 0K
描述： IC RE-TIMER OCTAL 192-BGA
標準包裝： 90
類型： 時鐘和數(shù)據(jù)恢復（CDR），多路復用器
PLL： 無
輸入： CML
輸出： CML，CMOS
電路數(shù)： 1
比率 - 輸入:輸出： 8:8
差分 - 輸入:輸出： 是/是
頻率 - 最大： 1.59Gbps
電源電壓： 1.3 V ~ 2.5 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 192-EBGA
供應商設備封裝： 192-EBGA-B（17x17）
包裝： 托盤
37
Note (1): The values may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details).
Note (2): If ‘Indirect DOM Enable’ is set, then the DOM A/D and Flag values are loaded from the I2C spaces pointed to by the Indirect Mode values in Table 53 and
Table 54, and ‘Representative’ controls which lane’s A/D values will appear in 1.A060:D’h. If not, then ‘Representative’ has no effect, and the full DOM area is
updated from a single DOM device. See “DOM Registers” on page 16 for details.
Note (1): See Table 38 and Table 51 for these registers.
Note (2): These are the Default values. The value in 1.C018’h may be overwritten by the Auto-Configure operation
Note (1): The values may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details).
Table 51. DOM CONTROL REGISTER
MDIO REGISTER ADDRESS = 1.49176 (1.C018’h)
BIT
NAME
SETTING
DEFAULT(1)
R/W
DESCRIPTION
1.49176.15:6
Reserved
1.49176.5
Test Control
0’b
R/W
User must keep at 0.
1.49176.4:3
DOM Update period
00’h
R/W
Controls rates at which DOM A/D values are
updated
1.49176.2
Indirect DOM Enable
1 = Enable
0 = Disable
0’b(2)
R/W
Enable updates from four DOM devices. See
1.49176.1:0
Representative
Lane value
00’b(2)
R/W
Select Lane for 1.A060:D’h
Table 52. DOM PERIODIC UPDATE WAITING TIME VALUES
(Approximate, based on REF_CLOCK = 156.25 MHz; default underlined)
1.41216.1:0
(1.A100’h.1:0) BITS(1)
1.49176.4:3 (1.C018’h) BITS(1)
00(2)
01
10
11
00
N/A
01
800ms
1000ms
1300ms
1600ms
10
400ms
500ms
600ms
700ms
11(2)
100ms(2)
150ms
200ms
300ms
Table 53. DOM INDIRECT MODE START ADDRESS REGISTERS
MDIO REGISTER ADDRESSES = 1.49177:8 (1.C019:1A’h)
BIT
NAME
SETTING
DEFAULT(1)
R/W
DESCRIPTION
1.49177.15:8
Lane 3 DOM
Start Address
60’h
R/W
Start address to read A/D values
from DOM monitor device of respective lane
1.49177.7:0
Lane 2 DOM
Start Address
60’h
R/W
1.49178.15:8
Lane 1 DOM
Start Address
60’h
R/W
1.49178.7:0
Lane 0 DOM
Start Address
60’h
R/W
Table 54. DOM INDIRECT MODE DEVICE ADDRESS REGISTERS
MDIO REGISTER ADDRESSES = 1.49179:80 (1.C01B:1C’h)
BIT
NAME
SETTING
DEFAULT(1)
R/W
DESCRIPTION
1.49179.15:9
Lane 3 DOM
Device Address
54’h
R/W
Note: I2C Device address to read A/D values
from DOM monitor device of respective lane is
twice set value. Thus ‘Default’ column
addresses are A8’h, A6’h A4’h and A2’h for
Lanes 3, 2, 1 & 0 respectively. LSB reflects
‘Read’ operation value
1.49179.8
Not used, Set by current operation
1.49179.7:1
Lane 2 DOM
Device Address
53’h
R/W
1.49179.0
Not used, Set by current operation
1.49180.15:8
Lane 1 DOM
Device Address
52’h
R/W
1.49180.7
Not used, Set by current operation
1.49180.7:1
Lane 0 DOM
Device Address
51’h
R/W
1.49180.0
Not used, Set by current operation
BBT3821
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