Note (1): These 1-byte register values are merely copied by the BBT3821 from the I2
參數(shù)資料
型號(hào)： BBT3821LP-JH
廠商： Intersil
文件頁(yè)數(shù)： 25/75頁(yè)
文件大小： 0K
描述： IC RE-TIMER OCTAL 192-BGA
標(biāo)準(zhǔn)包裝： 90
類型： 時(shí)鐘和數(shù)據(jù)恢復(fù)（CDR），多路復(fù)用器
PLL： 無(wú)
輸入： CML
輸出： CML，CMOS
電路數(shù)： 1
比率 - 輸入:輸出： 8:8
差分 - 輸入:輸出： 是/是
頻率 - 最大： 1.59Gbps
電源電壓： 1.3 V ~ 2.5 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 192-EBGA
供應(yīng)商設(shè)備封裝： 192-EBGA-B（17x17）
包裝： 托盤
31
Note (1): These 1-byte register values are merely copied by the BBT3821 from the I2C address space on RESET (if enabled), on demand, or periodically under the
control of Register 1.A100’h (Table 38).
Note (2): If the ‘Indirect DOM Enable’ bit (Register bit 1.C018’h.2 Table 51) is not set, a four-lane external DOM device is expected to determine the “Farthest out of
range” or “Representative” values for these registers, according to the rules of Note 1 to Table 28 in the XENPAK MSA Rev 3.0 specification. A single one-lane
DOM device system will provide the values from the single DOM device here only. If the ‘Indirect DOM Enable’ bit is set, “Representative” is defined by
Register bits 1.C018’h.1:0 (Table 51), and the values from the specified lane’s DOM are entered here also.
Note (3): If the ‘Indirect DOM Enable’ bit (Register bit 1.C018’h.2 Table 51) is not set, a four-lane external DOM device is expected to provide the Lane-by-Lane data.
For a single one-lane DOM device system these values are 00’h. The Lane-by-Lane data is obtained from the I2C address space via the pointers defined in
Registers 1.C019:C’h (Table 53 & Table 54), if the ‘Indirect DOM Enable’ bit is set (Register 1.C018’h Table 51).
Note (1): This 1-byte register value is merely copied by the BBT3821 from the I2C address space on Power-up or RESET, or on a periodic or on-demand direct DOM
update operation (i.e. with Register bit 1.C018’h.2 Table 51 not set) under the control of Register 1.A100’h (Table 38). The BBT3821 takes no action as a result
of the values copied.
Note (2): Assumes NVR/DOM read succeeds
1.41170:1
1.A0D2:3
210:211
Reserved
RO
MSB:LSB
1.41172:3
1.A0D4:5
212:213
Lane 1 Laser Bias Current(3)
RO
MSB:LSB
1.41174:5
1.A0D6:7
214:215
Lane 1 Laser Output Power(3)
RO
MSB:LSB
1.41176:7
1.A0D8:9
216:217
Lane 1 Receive Optical Power(3)
RO
MSB:LSB
1.41178:83
1.A0DA:F
218:223
Reserved
1.41184:5
1.A0E0:1
224:225
Lane 2 Transceiver Temperature (3)
RO
MSB:LSB
1.41186:7
1.A0E2:3
226:227
Reserved
RO
MSB:LSB
1.41188:9
1.A0E4:5
228:229
Lane 2 Laser Bias Current(3)
RO
MSB:LSB
1.41190:1
1.A0E6:7
230:231
Lane 2 Laser Output Power(3)
RO
MSB:LSB
1.41192:3
1.A0E8:9
232:233
Lane 2 Receive Optical Power(3)
RO
MSB:LSB
1.41194:9
1.A0EA:F
234:239
Reserved
1.41200:1
1.A0F0:1
240:241
Lane 3 Transceiver Temperature (3)
RO
MSB:LSB
1.41202:3
1.A0F2:3
242:243
Reserved
RO
MSB:LSB
1.41204:5
1.A0F4:5
244:245
Lane 3 Laser Bias Current(3)
RO
MSB:LSB
1.41206:7
1.A0F6:7
246:247
Lane 3 Laser Output Power(3)
RO
MSB:LSB
1.41208:9
1.A0F8:9
228:249
Lane 3 Receive Optical Power(3)
RO
MSB:LSB
1.41210:5
1.A0FA:F
250:255
Reserved
Table 33. XENPAK DOM MONITORED A/D VALUES REGISTER COPY (Continued)
MDIO XENPAK/XPAK/X2 DOM REGISTER ADDRESSES = 1.41056:41069 & 1.41152:41215 (1.A060:A06D’h & 1.A0C0:A0FF)
BYTE ADDRESS
MEMORY
ADDRESS
DESCRIPTION(1)
DEFAULT
R/W
DETAILS
DEC
HEX
Table 34. XENPAK OPTIONAL DOM STATUS BITS REGISTER
MDIO REGISTER, ADDRESS = 1.41070 (1.A06E’h)
BIT
NAME
SETTING
DEFAULT
R/W
DESCRIPTION(1)
1.41070.15:1
Reserved
0000’h
1.41070.0
Data_Ready_Bar
1 = Not Ready
0 = Ready
0’b(2)
RO
High during power-up and first
NVR/DOM read. After that set low.
BBT3821
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