Note (1): These bits are latched high on any LOS condition detected. They are reset low on being read. Auto-Configure Register List Tabl" />
參數(shù)資料
型號： BBT3821LP-JH
廠商： Intersil
文件頁數(shù)： 47/75頁
文件大?。?/td> 0K
描述： IC RE-TIMER OCTAL 192-BGA
標(biāo)準(zhǔn)包裝： 90
類型： 時鐘和數(shù)據(jù)恢復(fù)（CDR），多路復(fù)用器
PLL： 無
輸入： CML
輸出： CML，CMOS
電路數(shù)： 1
比率 - 輸入:輸出： 8:8
差分 - 輸入:輸出： 是/是
頻率 - 最大： 1.59Gbps
電源電壓： 1.3 V ~ 2.5 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 192-EBGA
供應(yīng)商設(shè)備封裝： 192-EBGA-B（17x17）
包裝： 托盤
51
Note (1): These bits are latched high on any LOS condition detected. They are reset low on being read.
Auto-Configure Register List
Table 89. PHY XS OUTPUT AND TEST FUNCTION CONTROL REGISTER
MDIO REGISTER ADDRESS = 4.49160 (4.C008’h)
BIT
NAME
SETTING
DEFAULT
R/W
DESCRIPTION
4.49160.15:14
Reserved
10’b
R/W
Test Function, do not alter
4.49160.13
ENA_3
Enable Lane 3 O/P
1’b
R/W
0 = disable
4.49160.12:10
Reserved
010’b
R/W
Test Function, do not alter
4.49160.9
ENA_2
Enable Lane 2 O/P
1’b
R/W
0 = disable
4.49160.8:6
Reserved
010’b
R/W
Test Function, do not alter
4.49160.5
ENA_1
Enable Lane 1 O/P
1’b
R/W
0 = disable
4.49160.12:10
Reserved
010’b
R/W
Test Function, do not alter
4.49160.1
ENA_0
Enable Lane 0 O/P
1’b
R/W
0 = disable
4.49160.0
Reserved
0’b
R/W
Test Function, do not alter
Table 90. PHY XS STATUS 4 LOS DETECTOR REGISTER
MDIO REGISTER ADDRESS = 4.49162 (4.C00A’h)
BIT
NAME
SETTING
DEFAULT
R/W
DESCRIPTION
4.49162.15:4
Reserved
00’b
4.49162.3
PHY_LOS_3
1 = Signal less than threshold
0 = Signal greater than threshold
0’b
RO/LH(1) Loss Of Signal for lane 3
4.49162.2
PHY_LOS_2
0’b
Loss Of Signal for lane 2
4.49162.1
PHY_LOS_1
0’b
Loss Of Signal for lane 1
4.49162.0
PHY_LOS_0
0’b
Loss Of Signal for lane 0
Table 91. PHY XS CONTROL REGISTER 4
MDIO REGISTER ADDRESS = 4.49163 (4.C00B’h)
BIT
NAME
SETTING
DEFAULT
R/W
DESCRIPTION
4.49163.15:2
Reserved
00’h
4.49163.1
TXCLK20
0 = disable 1 = enable
0’b
R/W
TXCLK20 pin output
4.49163.0
Test
Internal
0’b
R/W
User must keep at 0’b
Table 92. AUTO-CONFIGURE REGISTERS
Auto-configure Pointer is (S), Auto-configure Size is (N), from 1.8106’h & 1.8105’h respectively
NVR ADDRESS
TARGET REGISTER BITS ADDRESS (1)
TARGET NAME(1)
DETAILS
DEC
HEX
DEC
HEX
S + 0
4.49158.[3:0]
4.C006.[3:0]
PHY XS Equalizer Value
S + 1
4.49157.[7:0]
4.C005.[7:0]
PHY XS Pre-emphasis Lanes 1:0
S + 2
4.49157.[15:8]
4.C005.[15:8]
PHY XS Pre-emphasis Lanes 3:2
S + 3
1.49158.[3:0]
1.C006.[3:0]
PMA/PMD Equalizer Value
S + 4
1.49157.[7:0]
1.C005.[7:0]
PMA/PMD Pre-emphasis Lanes 1:0
S + 5
1.49157.[15:8]
1.C005.[15:8]
PMA/PMD Pre-emphasis Lanes 3:2
S + 6
1.36864.[6:0].
1.9000.[6:0]
LASI RX Alarm Control
BBT3821
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