Full Duplex Operation (Independent Serial Receiv" />
參數(shù)資料
型號(hào): ATTINY2313A-SUR
廠商: Atmel
文件頁數(shù): 25/172頁
文件大?。?/td> 0K
描述: MCU AVR 2KB FLASH 20MHZ 20SOIC
產(chǎn)品培訓(xùn)模塊: tinyAVR Introduction
標(biāo)準(zhǔn)包裝: 1,000
系列: AVR® ATtiny
核心處理器: AVR
芯體尺寸: 8-位
速度: 20MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 18
程序存儲(chǔ)器容量: 2KB(1K x 16)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 128 x 8
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-SOIC(0.295",7.50mm 寬)
包裝: 帶卷 (TR)
其它名稱: ATTINY2313A-SUR-ND
120
8246B–AVR–09/11
ATtiny2313A/4313
14. USART
14.1
Features
Full Duplex Operation (Independent Serial Receive and Transmit Registers)
Asynchronous or Synchronous Operation
Master or Slave Clocked Synchronous Operation
High Resolution Baud Rate Generator
Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits
Odd or Even Parity Generation and Parity Check Supported by Hardware
Data OverRun Detection
Framing Error Detection
Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter
Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete
Multi-processor Communication Mode
Double Speed Asynchronous Communication Mode
14.2
Overview
The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a
highly flexible serial communication device.
A simplified block diagram of the USART Transmitter is shown in Figure 14-1. CPU accessible
I/O Registers and I/O pins are shown in bold.
Figure 14-1. USART Block Diagram
Note:
pin placement.
PARITY
GENERATOR
UBRR[H:L]
UDR (Transmit)
UCSRA
UCSRB
UCSRC
BAUD RATE GENERATOR
TRANSMIT SHIFT REGISTER
RECEIVE SHIFT REGISTER
RxD
TxD
PIN
CONTROL
UDR (Receive)
PIN
CONTROL
XCK
DATA
RECOVERY
CLOCK
RECOVERY
PIN
CONTROL
TX
CONTROL
RX
CONTROL
PARITY
CHECKER
DATA
BUS
OSC
SYNC LOGIC
Clock Generator
Transmitter
Receiver
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