參數(shù)資料
型號(hào)： ATTINY2313A-SUR
廠商： Atmel
文件頁數(shù)： 110/172頁
文件大?。?/td> 0K
描述： MCU AVR 2KB FLASH 20MHZ 20SOIC
產(chǎn)品培訓(xùn)模塊： tinyAVR Introduction
標(biāo)準(zhǔn)包裝： 1,000
系列： AVR® ATtiny
核心處理器： AVR
芯體尺寸： 8-位
速度： 20MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 18
程序存儲(chǔ)器容量： 2KB（1K x 16）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 128 x 8
RAM 容量： 128 x 8
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 20-SOIC（0.295"，7.50mm 寬）
包裝： 帶卷 (TR)
其它名稱： ATTINY2313A-SUR-ND
42
8246B–AVR–09/11
ATtiny2313A/4313
8.2.4
Watchdog Reset
When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On
the falling edge of this pulse, the delay timer starts counting the Time-out period t
TOUT. See
“Interrupts” on page 48 for details on operation of the Watchdog Timer.
Figure 8-6.
Watchdog Reset During Operation
8.3
Internal Voltage Reference
ATtiny2313A/4313 features an internal bandgap reference. This reference is used for Brown-out
Detection, and it can be used as an input to the Analog Comparator. The bandgap voltage varies
with supply voltage and temperature.
8.3.1
Voltage Reference Enable Signals and Start-up Time
The voltage reference has a start-up time that may influence the way it should be used. The
start-up time is given in “System and Reset Characteristics” on page 201. To save power, the
reference is not always turned on. The reference is on during the following situations:
1.
When the BOD is enabled (by programming the BODLEVEL [2..0] Fuse).
2.
When the internal reference is connected to the Analog Comparator (by setting the
ACBG bit in ACSR).
Thus, when the BOD is not enabled, after setting the ACBG bit, the user must always allow the
reference to start up before the output from the Analog Comparator. To reduce power consump-
tion in Power-down mode, the user can avoid the three conditions above to ensure that the
reference is turned off before entering Power-down mode.
8.4
Watchdog Timer
The Watchdog Timer is clocked from an On-chip Oscillator which runs at 128 kHz. By controlling
the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as shown in Table
8-3 on page 47. The WDR – Watchdog Reset – instruction resets the Watchdog Timer. The
Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs. Ten different
clock cycle periods can be selected to determine the reset period. If the reset period expires
without another Watchdog Reset, the ATtiny2313A/4313 resets and executes from the Reset
Vector. For timing details on the Watchdog Reset, refer to Table 8-3 on page 47.
CK
CC
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ATTINY2313V_06 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-bit Microcontroller with 2K Bytes In-System Programmable Flash
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