參數資料
型號： AT89C51IC2-SLSIL
廠商： Atmel
文件頁數： 6/140頁
文件大?。?/td> 0K
描述： IC 8051 MCU FLASH 32K 44PLCC
標準包裝： 27
系列： 89C
核心處理器： 8051
芯體尺寸： 8-位
速度： 40MHz
連通性： I²C，SPI，UART/USART
外圍設備： POR，PWM，WDT
輸入/輸出數： 34
程序存儲器容量： 32KB（32K x 8）
程序存儲器類型： 閃存
RAM 容量： 1.25K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 3.6 V
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-LCC（J 形引線）
包裝： 管件
103
AT89C51IC2
4301D–8051–02/08
Table 80. WDTPRG Register
WDTPRG - Watchdog Timer Out Register (0A7h)
Reset value XXXX X000
WDT During Power Down
and Idle
In Power Down mode the oscillator stops, which means the WDT also stops. While in
Power Down mode the user does not need to service the WDT. There are 2 methods of
exiting Power Down mode: by a hardware reset or via a level activated external inter-
rupt which is enabled prior to entering Power Down mode. When Power Down is exited
with hardware reset, servicing the WDT should occur as it normally should whenever the
AT89C51IC2 is reset. Exiting Power Down with an interrupt is significantly different. The
interrupt is held low long enough for the oscillator to stabilize. When the interrupt is
brought high, the interrupt is serviced. To prevent the WDT from resetting the device
while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high.
It is suggested that the WDT be reset during the interrupt service routine.
To ensure that the WDT does not overflow within a few states of exiting of powerdown, it
is better to reset the WDT just before entering powerdown.
In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the
AT89C51IC2 while in Idle mode, the user should always set up a timer that will periodi-
cally exit Idle, service the WDT, and re-enter Idle mode.
7
6
5
4
3
2
1
0
-
S2
S1
S0
Bit
Number
Bit
Mnemonic Description
7
-
Reserved
The value read from this bit is undetermined. Do not try to set this bit.
6
-
5
-
4
-
3
-
2
S2
WDT Time-out select bit 2
1
S1
WDT Time-out select bit 1
0
S0
WDT Time-out select bit 0
S2
S1 S0Selected Time-out
0
00
(214 - 1) machine cycles, 16. 3 ms @ F
OSCA =12 MHz
0
01
(215 - 1) machine cycles, 32.7 ms @ FOSCA=12 MHz
0
10 (216 - 1) machine cycles, 65. 5 ms @ F
OSCA=12 MHz
0
11
(217 - 1) machine cycles, 131 ms @ F
OSCA=12 MHz
1
00
(218 - 1) machine cycles, 262 ms @ FOSCA=12 MHz
1
01 (219 - 1) machine cycles, 542 ms @ F
OSCA=12 MHz
1
10
(220 - 1) machine cycles, 1.05 s @ F
OSCA=12 MHz
1
11
(221 - 1) machine cycles, 2.09 s @ FOSCA=12 MHz
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