參數資料
型號: AT89C51IC2-SLSIL
廠商: Atmel
文件頁數: 120/140頁
文件大?。?/td> 0K
描述: IC 8051 MCU FLASH 32K 44PLCC
標準包裝: 27
系列: 89C
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: I²C,SPI,UART/USART
外圍設備: POR,PWM,WDT
輸入/輸出數: 34
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
RAM 容量: 1.25K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LCC(J 形引線)
包裝: 管件
80
AT89C51IC2
4301D–8051–02/08
Keyboard Interface
The AT89C51IC2 implements a keyboard interface allowing the connection of a
8 x n matrix keyboard. It is based on 8 inputs with programmable interrupt capability on
both high or low level. These inputs are available as alternate function of P1 and allow to
exit from idle and power down modes.
The keyboard interface interfaces with the C51 core through 3 special function registers:
KBLS, the Keyboard Level Selection register (Table 63), KBE, The Keyboard interrupt
Enable register (Table 62), and KBF, the Keyboard Flag register (Table 61).
Interrupt
The keyboard inputs are considered as 8 independent interrupt sources sharing the
same interrupt vector. An interrupt enable bit (KBD in IEN1) allows global enable or dis-
able of the keyboard interrupt (see Figure 33). As detailed in Figure 34 each keyboard
input has the capability to detect a programmable level according to KBLS.x bit value.
Level detection is then reported in interrupt flags KBF.x that can be masked by software
using KBE.x bits.
This structure allow keyboard arrangement from 1 by n to 8 by n matrix and allow usage
of P1 inputs for other purpose.
Figure 33. Keyboard Interface Block Diagram
Figure 34. Keyboard Input Circuitry
Power Reduction Mode
P1 inputs allow exit from idle and power down modes as detailed in Section “Power
P1:x
KBE.x
KBF.x
KBLS.x
0
1
Vcc
Internal Pullup
P1.0
Keyboard Interface
Interrupt Request
KBD
IEN1
Input Circuitry
P1.1
Input Circuitry
P1.2
Input Circuitry
P1.3
Input Circuitry
P1.4
Input Circuitry
P1.5
Input Circuitry
P1.6
Input Circuitry
P1.7
Input Circuitry
KBDIT
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