1. Operating ICC is measured with all output pi" />
參數(shù)資料
型號: AT89C51IC2-SLSIL
廠商: Atmel
文件頁數(shù): 34/140頁
文件大?。?/td> 0K
描述: IC 8051 MCU FLASH 32K 44PLCC
標(biāo)準(zhǔn)包裝: 27
系列: 89C
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 34
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
RAM 容量: 1.25K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LCC(J 形引線)
包裝: 管件
129
AT89C51IC2
4301D–8051–02/08
Notes:
1. Operating ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns (see Figure 56.), VIL =
VSS + 0.5V,
VIH = VCC - 0.5V; XTAL2 N.C.; EA = RST = Port 0 = VCC. ICC would be slightly higher if a crystal oscillator used (see Figure
2. Idle ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns, VIL = VSS + 0.5V, VIH = VCC -
0.5V; XTAL2 N.C; Port 0 = VCC; EA = RST = VSS (see Figure 54).
3. Power Down ICC is measured with all output pins disconnected; EA = VSS, PORT 0 = VCC; XTAL2 NC.; RST = VSS (see Fig-
4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLs of ALE and Ports 1
and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0
transitions during bus operation. In the worst cases (capacitive loading 100pF), the noise pulse on the ALE line may exceed
0.45V with maxi VOL peak 0.6V. A Schmitt Trigger use is not necessary.
5. Typical are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and
5V.
6. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum IOL per 8-bit port:
Port 0: 26 mA
Ports 1, 2 and 3: 15 mA
Maximum total IOL for all output pins: 71 mA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
7. For other values, please contact your sales office.
8. Icc Flash Write operation current while an on-chip flash page write is on going.
9. Flash Retention is guaranteed with the same formula for VCC Min down to 0.
VOH1
Output High Voltage, port 0, ALE, PSEN
VCC - 0.3
VCC - 0.7
VCC - 1.5
V
VCC = 5V ± 10%
IOH = -200 A
IOH = -3.2 mA
IOH = -7.0 mA
0.9 VCC
V
VCC = 2.7V to 5.5V
IOH = -10 A
RRST
RST Pulldown Resistor
50
200(5)
250
k
IIL
Logical 0 Input Current ports 1, 2, 3, 4 and 5
-50
A
VIN = 0.45V
ILI
Input Leakage Current for P0 only
±
10
A
0.45V < VIN < VCC
ITL
Logical 1 to 0 Transition Current, ports 1, 2, 3, 4
-650
A
VIN = 2.0V
C
IO
Capacitance of I/O Buffer
10
pF
Fc = 3 MHz
TA = 25°C
I
PD
Power Down Current
100
150
A
4.5V < V
CC < 5.5V
(3)
I
CCOP
Power Supply Current on normal mode
0.4 x Frequency (MHz) + 5
mA
V
CC = 5.5V
(1)
I
CCIDLE
Power Supply Current on idle mode
0.3 x Frequency (MHz) + 5
mA
V
CC = 5.5V
(1)
I
CCProg
Power Supply Current during flash Write / Erase
0.4 x
Frequency
(MHz) + 20
mA
V
CC = 5.5V
(8)
TA = -40°C to +85°C; VSS = 0V;
VCC =2.7V to 5.5V and F = 0 to 40 MHz (both internal and external code execution)
VCC =4.5V to 5.5V and F = 0 to 60 MHz (internal code execution only) (Continued)
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
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