參數(shù)資料
型號(hào)： ASDP-21365BBCZ-1AA
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： SHARC Processor
中文描述： 16-BIT, 55.55 MHz, OTHER DSP, PBGA136
封裝： MO-205AE, BGA-136
文件頁(yè)數(shù)： 30/52頁(yè)
文件大?。?/td> 1320K
代理商： ASDP-21365BBCZ-1AA
Rev. A
|
Page 30 of 52
|
December 2006
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Table 25. 16-Bit Memory Write Cycle
Parameter
Switching Characteristics
t
ALEW
t
ADAS
1
t
ALERW
t
RWALE
t
WRH
2
t
ADAH
1
t
WW
t
DWS
t
DWH
D = (data cycle duration = the value set by the PPDUR Bits (5–1) in the PPCTL register)
×
t
PCLK
.
H = t
PCLK
(if a hold cycle is specified, else H = 0)
F = 7
×
t
PCLK
(if FLASH_MODE is set, else F = 0). If FLASH_MODE is set, D must be
≥
9
×
t
PCLK
.
t
PCLK
= (peripheral) clock period = 2
×
t
CCLK
Min
Max
Unit
ALE Pulse Width
AD15–0 Address Setup Before ALE Deasserted
ALE Deasserted to Write Asserted
Write Deasserted to ALE Asserted
Delay Between WR Rising Edge to Next WR Falling Edge
AD15–0 Address Hold After ALE Deasserted
WR Pulse Width
AD15–0 Data Setup Before WR High
AD15–0 Data Hold After WR High
2 × t
PCLK
– 2.0
t
PCLK
– 2.5
2 × t
PCLK
– 3.8
H + 0.5
F + H + t
PCLK
– 2.3
t
PCLK
– 2.3
D – F – 2.0
D – F + t
PCLK
– 4.0
H
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
On reset, ALE is an active high cycle. However, it can be configured by software to be active low.
2
This parameter is only available when in EMPP = 0 mode.
Figure 21. Write Cycle for 16-Bit Memory Timing
AD15
-
0
VALID
ADDRESS
VALID DATA
t
ADAS
ALE
RD
WR
t
ADAH
t
WRH
t
RWALE
t
ALEW
t
ALERW
t
WW
t
DWS
t
DWH
VALID DATA
VALID
ADDRESS
NOTE: FOR 16-BIT MEMORY WRITES, WHEN EMPP
WHEN EMPP = 0, MULTIPLE
WR
PULSES OCCUR BETWEEN ALE CYCLES. FOR COMPLETE INFORMATION,
SEE THE ADSP-2136X SHARC PROCESSOR HARDWARE REFERENCE.
0, ONLY ONE
WR
PULSE OCCURS BETWEEN ALE CYCLES.
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