參數(shù)資料
型號(hào)： ASDP-21365BBCZ-1AA
廠商： ANALOG DEVICES INC
元件分類(lèi)： 數(shù)字信號(hào)處理
英文描述： SHARC Processor
中文描述： 16-BIT, 55.55 MHz, OTHER DSP, PBGA136
封裝： MO-205AE, BGA-136
文件頁(yè)數(shù)： 11/52頁(yè)
文件大小： 1320K
代理商： ASDP-21365BBCZ-1AA
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Rev. A
|
Page 11 of 52
|
December 2006
drag of the mouse and examine runtime stack and heap usage.
The expert linker is fully compatible with the existing linker def-
inition file (LDF), allowing the developer to move between the
graphical and textual environments.
In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide
range of tools supporting the SHARC processor family. Hard-
ware tools include SHARC processor PC plug-in cards. Third
party software tools include DSP libraries, real-time operating
systems, and block diagram design tools.
Designing an Emulator-Compatible DSP Board(Target)
The Analog Devices family of emulators are tools that every
DSP developer needs to test and debug hardware and software
systems. Analog Devices has supplied an IEEE 1149.1 JTAG test
access port (TAP) on each JTAG processor. Nonintrusive in-
circuit emulation is assured by the use of the processor’s JTAG
interface—the emulator does not affect target system loading or
timing. The emulator uses the TAP to access the internal fea-
tures of the processor, allowing the developer to load code, set
breakpoints, observe variables, observe memory, and examine
registers. The processor must be halted to send data and com-
mands, but once an operation has been completed by the
emulator, the DSP system is set running at full speed with no
impact on system timing.
To use these emulators, the target board must include a header
that connects the DSP’s JTAG port to the emulator.
For details on target board design issues including mechanical
layout, single processor connections, multiprocessor scan
chains, signal buffering, signal termination, and emulator pod
logic, see the
EE-68: Analog Devices JTAG Emulation Technical
Reference
on the Analog Devices website (
www.analog.com
)—
use site search on “EE-68.” This document is updated regularly
to keep pace with improvements to emulator support.
Evaluation Kit
Analog Devices offers a range of EZ-KIT Lite
evaluation plat-
forms to use as a cost-effective method to learn more about
developing or prototyping applications with Analog Devices
processors, platforms, and software tools. Each EZ-KIT Lite
platform includes an evaluation board along with an evaluation
suite of the VisualDSP++ development and debugging environ-
ment with the C/C++ compiler, assembler, and linker. Also
included are sample application programs, power supply, and a
USB cable. All evaluation versions of the software tools are lim-
ited for use only with the EZ-KIT Lite product.
The USB controller on the EZ-KIT Lite board connects the
board to the USB port of the user’s PC, enabling the
VisualDSP++ evaluation suite to emulate the on-board proces-
sor in-circuit. This permits the customer to download, execute,
and debug programs for the EZ-KIT Lite system. It also allows
in-circuit programming of the on-board flash device to store
user-specific boot code, enabling the board to run as a stand-
alone unit without being connected to the PC.
With a full version of VisualDSP++ installed (sold separately),
engineers can develop software for the EZ-KIT Lite or any cus-
tom defined system. Connecting one of Analog Devices’ JTAG
emulators to the EZ-KIT Lite board enables high speed, non-
intrusive emulation.
ADDITIONAL INFORMATION
This data sheet provides a general overview of the
ADSP-2136x architecture and functionality. For detailed infor-
mation on the ADSP-2136x family core architecture and
instruction set, refer to the
ADSP-2136x SHARC Processor
Hardware Reference
and the
ADSP-2136x SHARC Processor
Programming Reference
.
EZ-KIT Lite is a registered trademark of Analog Devices, Inc.
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