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參數(shù)資料
| 型號： | ASDP-21365WBBCZ-1A |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | SHARC Processor |
| 中文描述： | 16-BIT, 55.55 MHz, OTHER DSP, PBGA136 |
| 封裝： | MO-205AE, BGA-136 |
| 文件頁數(shù)： | 1/52頁 |
| 文件大小： | 1320K |
| 代理商： | ASDP-21365WBBCZ-1A |
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a
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
SHARC
Processor
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel : 781.329.4700
Fax: 781.461.3113
2006 Analog Devices, Inc. All rights reserved.
www.analog.com
SUMMARY
High performance, 32-bit/40-bit, floating-point processor
optimized for high performance processing
Single-instruction, multiple-data (SIMD) computational
architecture
On-chip memory—3M bit of on-chip SRAM
Code compatible with all other members of the SHARC family
The ADSP-2136x processors are available with a 333 MHz
core instruction rate and unique peripherals such as the digi-
tal audio interface, S/PDIF transceiver, DTCP (digital
transmission content protection protocol), serial ports,
8-channel asynchronous sample rate converter, precision
clock generators, and more. For complete ordering informa-
tion, see
Ordering Guide on Page 52
.
Figure 1. Functional Block Diagram—Processor Core
ADDR
DATA
IOD
ADDR
DATA
IOA
ADDR
DATA
IOA
SRAM
1M BIT
ROM
2M BIT
SRAM
0.5M BIT
BLOCK 0
BLOCK 1
BLOCK 2
BLOCK 3
ADDR
DATA
IOA
IOP REGISTERS
(MEMORY MAPPED)
I/O PROCESSOR
AND PERIPHERALS
6
JTAG TEST AND EMULATION
32
PM ADDRESS BUS
DM ADDRESS BUS
32
PM DATA BUS
DM DATA BUS
64
64
PX REGISTER
PROCESSING
ELEMENT
(PEY)
PROCESSING
ELEMENT
(PEX)
TIMER
INSTRUCTION
CACHE
32-BIT
48-BIT
DAG1
8 4 32
DAG2
8 4 32
CORE PROCESSOR
PROGRAM
SEQUENCER
SRAM
1M BIT
ROM
2M BIT
SIGNAL
ROUTING
UNIT
SRAM
0.5M BIT
4 BLOCKS OF ON-CHIP MEMORY
IOD
IOA
IOD
IOD
SPI
SPORTS
IDP
PCG
TIMERS
SRC
SPDIF
DTCP
S
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