參數(shù)資料
型號(hào)： ASDP-21365BBCZ-1AA
廠商： ANALOG DEVICES INC
元件分類(lèi)： 數(shù)字信號(hào)處理
英文描述： SHARC Processor
中文描述： 16-BIT, 55.55 MHz, OTHER DSP, PBGA136
封裝： MO-205AE, BGA-136
文件頁(yè)數(shù)： 28/52頁(yè)
文件大小： 1320K
代理商： ASDP-21365BBCZ-1AA
Rev. A
|
Page 28 of 52
|
December 2006
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Table 23. 16-Bit Memory Read Cycle
Parameter
Timing Requirements
t
DRS
t
DRH
Min
Max
Unit
AD15–0 Data Setup Before RD High
AD15–0 Data Hold After RD High
3.3
0
ns
ns
Switching Characteristics
t
ALEW
t
ADAS
1
t
ALERW
t
RRH
2
t
RWALE
t
RDDRV
t
ADAH
1
t
ALEHZ
1
t
RW
D = (data cycle duration = the value set by the PPDUR Bits (5–1) in the PPCTL register)
×
t
PCLK
H = t
PCLK
(if a hold cycle is specified, else H = 0)
F = 7
×
t
PCLK
(if FLASH_MODE is set, else F = 0)
t
PCLK
= (peripheral) clock period = 2
×
t
CCLK
ALE Pulse Width
AD15–0 Address Setup Before ALE Deasserted
ALE Deasserted to Read Asserted
Delay Between RD Rising Edge to Next Falling Edge
Read Deasserted to ALE Asserted
ALE Address Drive After Read High
AD15–0 Address Hold After ALE Deasserted
ALE Deasserted to Address/Data15–0 in High Z
RD Pulse Width
2 × t
PCLK
– 2.0
t
PCLK
– 2.5
2 × t
PCLK
– 3.8
H + t
PCLK
– 1.4
F + H + 0.5
F + H + t
PCLK
– 2.3
t
PCLK
– 2.3
t
PCLK
D – 2.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
PCLK
+ 3.0
1
On reset, ALE is an active high cycle. However, it can be configured by software to be active low.
2
This parameter is only available when in EMPP = 0 mode.
Figure 19. Read Cycle for 16-Bit Memory Timing
AD15
-
0
WR
t
DRS
t
DRH
t
ALEHZ
t
ADAH
t
ADAS
VALID ADDRESS
VALID DATA
VALID DATA
t
ALEW
t
RW
t
ALERW
t
RRH
ALE
RD
t
RWALE
t
RDDRV
VALID
ADDRESS
NOTE: FOR 16-BIT MEMORY READS, WHEN EMPP
WHEN EMPP = 0, MULTIPLE
RD
PULSES OCCUR BETWEEN ALE CYCLES. FOR COMPLETE INFORMATION,
SEE THE ADSP-2136X SHARC PROCESSOR HARDWARE REFERENCE.
0, ONLY ONE
RD
PULSE OCCURS BETWEEN ALE CYCLES.
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