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參數(shù)資料
| 型號(hào)： | ASDP-21365BBCZ-1AA |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | SHARC Processor |
| 中文描述： | 16-BIT, 55.55 MHz, OTHER DSP, PBGA136 |
| 封裝： | MO-205AE, BGA-136 |
| 文件頁數(shù)： | 26/52頁 |
| 文件大?。?/td> | 1320K |
| 代理商： | ASDP-21365BBCZ-1AA |
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Rev. A
|
Page 26 of 52
|
December 2006
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Memory Read—Parallel Port
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) when the ADSP-2136x
is accessing external memory space.
Table 22. 8-Bit Memory Read Cycle
Parameter
Timing Requirements
t
DRS
1
t
DRH
t
DAD
1
Min
Max
Unit
AD7–0 Data Setup Before RD High
AD7–0 Data Hold After RD High
AD15–8 Address to AD7–0 Data Valid
3.3
0
ns
ns
ns
D + t
PCLK
– 5.0
Switching Characteristics
t
ALEW
t
ADAS
2
t
RRH
ALE Pulse Width
AD15–0 Address Setup Before ALE Deasserted
Delay Between RD Rising Edge to Next
Falling Edge
ALE Deasserted to Read Asserted
Read Deasserted to ALE Asserted
AD15–0 Address Hold After ALE Deasserted
ALE Deasserted to AD7–0 Address in High Z
RD Pulse Width
AD7–0 ALE Address Drive After Read High
AD15–8 Address Hold After RD High
AD15–8 Address to RD High
D = (data cycle duration = the value set by the PPDUR Bits (5–1) in the PPCTL register)
×
t
PCLK
H = t
PCLK
(if a hold cycle is specified, else H = 0)
F = 7
×
t
PCLK
(if FLASH_MODE is set, else F = 0)
t
PCLK
= (peripheral) clock period = 2
×
t
CCLK
2 × t
PCLK
– 2.0
t
PCLK
– 2.5
H + t
PCLK
– 1.4
ns
ns
ns
t
ALERW
t
RWALE
t
ADAH
2
t
ALEHZ
2
t
RW
t
RDDRV
t
ADRH
t
DAWH
2 × t
PCLK
– 3.8
F + H + 0.5
t
PCLK
– 2.3
t
PCLK
D – 2.0
F + H + t
PCLK
– 2.3
H
D + t
PCLK
– 4.0
ns
ns
ns
ns
ns
ns
ns
ns
t
PCLK
+ 3.0
1
The timing specified here is sufficient to satisfy either t
or t
as they are independent.
2
On reset, ALE is an active high cycle. However, it can be configured by software to be active low.
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