Figure 3. Block " />
參數(shù)資料
型號(hào)： AS8510-ASST-500
廠商： ams
文件頁(yè)數(shù)： 10/47頁(yè)
文件大?。?/td> 0K
描述： IC BATTERY MANAGEMENT 20-SSOP
產(chǎn)品培訓(xùn)模塊： AS8510 Data Acquisition IC
標(biāo)準(zhǔn)包裝： 1
類(lèi)型： 電池管理
輸入類(lèi)型： 模擬，數(shù)字
輸出類(lèi)型： 模擬，數(shù)字
接口： SPI 串行
電流 - 電源： 5.5mA
安裝類(lèi)型： 表面貼裝
封裝/外殼： 20-SSOP（0.209"，5.30mm 寬）
供應(yīng)商設(shè)備封裝： 20-SSOP
包裝： 標(biāo)準(zhǔn)包裝
其它名稱(chēng)： AS8510-ASST-500DKR
Revision 3.5
17 - 46
AS8510
Datasheet - Detailed Descr i p ti on
7.3 Digital Implementation of Measurement Path
Figure 3. Block Diagram of Digital Implementation
Figure 3 shows the digital implementation of the decimator and filter to process the 1-bit output of the Modulator. This block receives a 1-bit pulse
density modulated output (MOD_IN) from the second order sigma delta modulator along with the oversampling frequency clock (MOD_CLK).
The MOD_CLK directly goes to a clock division block, which generates chopper clock (CHOP_CLK). The CHOP_CLK can be one of 2kHz or
4kHz selected by Register CLK_REG in Table 33. The MOD_CLK can be either 1MHz or 2MHz. The Decimation is a two phase process. In the
first phase, the R1 down sampling rate can be obtained by selecting either 64 or 128 in Registers DECREG_R1_I, DECREG_R1_V in Table 33.
The 16-bit CIC1 output is dechopped with respect to CHOP_CLK. The output of Dechopper is passed through the CIC2 filter with a decimation
ratio of 1to 32768 in steps of power of 2. This output is then processed through a FIR or Moving Average (MA) filter. FIR Filter is provided to offer
matched low pass filter response typically required in lead acid battery sensor systems. MA filter is used to provide averaged output and the
number of samples for averaging can be any integer value from 1 to 15.
7.4 Modes of Operation
The device operates in four different modes, namely,
Normal Mode 1 (NOM1),
Normal Mode 2 (NOM2),
Standby Mode 1 (SBY1), and,
Standby Mode 2 (SBY2).
The Normal Modes are full-power modes with the exception that in Normal Mode 2, sampling is normally at a programmed lower frequency and
is increased to a higher rate only when a measured input signal level crosses the programmed threshold in the current measurement channel.
The Standby Modes are lower power modes. Sampling is normally at a very low frequency interval. In Standby Mode 2, data sampling can be
carried out only when the internal comparator detects the input current to be greater than the programmed threshold and it generates interrupt on
the INT pin.
The device enters into the “Stop” state on Power On. This is a state where in the data path is inactive and can be entered into from any of the
four Modes. The State transition Diagram involving the state of Stop and the four Modes is illustrated in the Figure 4.
CIC1
64/ 128
CLKDIVISION
BLOCK
Dechopper
FIR/MA
MOD_IN
MOD_CLK
DATAOUT
R1
R1=First decimationratio(64or 128)
R2=Seconddecimationratio(1to32768)
MOD_CLK
R1
CIC2
R2
FIR_MA_SEL
CHP_CLK
fmod / R1
fchop * 2
fchop * 2/ R2
fchop
fmod
fchop * 2/ R2
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