參數(shù)資料
型號(hào): AS8510-ASST-500
廠商: ams
文件頁(yè)數(shù): 18/47頁(yè)
文件大小: 0K
描述: IC BATTERY MANAGEMENT 20-SSOP
產(chǎn)品培訓(xùn)模塊: AS8510 Data Acquisition IC
標(biāo)準(zhǔn)包裝: 1
類型: 電池管理
輸入類型: 模擬,數(shù)字
輸出類型: 模擬,數(shù)字
接口: SPI 串行
電流 - 電源: 5.5mA
安裝類型: 表面貼裝
封裝/外殼: 20-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 20-SSOP
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: AS8510-ASST-500DKR
Revision 3.5
24 - 46
AS8510
Datasheet - Detailed Descr i p ti on
7.8.3 Read Command
For Read command C0=1. After the command code C0, the address of register to be read is provided from MSB to LSB. Then one or more data
bytes can be transferred from the SPI slave to the master, always from MSB to LSB. To transfer more bytes from consecutive addresses, SPI
master keeps CS signal LOW and SPI clock active as long as it desires to read data from the slave. Each bit of the command and address of the
frame is to be driven by the SPI master on the SPI clock transfer edge where SPI slave samples it on the next SPI clock edge.
Each bit of the data section of the frame is driven by the SPI slave on the SPI clock transfer edge and SPI master samples it on the next SPI
clock edge. These edges are determined as per Table 29 and examples of read command without and with address self-increment.
Figure 12. Protocol for Serial Data Read with Length = 1
Figure 13. Protocol for Serial Data Read with Length = 4
CS
SCLK
SDI
SDO
1
A6
A5
A4
A0
A1
A2
A3
D0
D1
D2
D3
D4
D5
D7
D6
Data D7 – D0 at
Address A4..A0 is
read here
CS
SCLK
SDI
SDO
1
A
6
A
5
A
4
A
0
A
1
A
2
A
3
D
0
D
1
D
2
D
3
D
4
D
5
D
7
D
6
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
Data D7-D0 at
Address A4-A0
is read here
Data D7-D0 at
Address A4-A0 +1
is read here
Data D7-D0 at
Address A4-A0 +2
is read here
Data D7-D0 at
Address A4-A0 +3
is read here
Data D7-D0 at
Address A4-A0 +4
is read here
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