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參數(shù)資料
| 型號(hào)： | AND8020D |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Termination of ECL Logic Devices with EF (Emitter Follower) OUTPUT Structure |
| 中文描述： | ECL邏輯器件的終止與英法（發(fā)射極跟隨器）輸出結(jié)構(gòu) |
| 文件頁(yè)數(shù)： | 8/18頁(yè) |
| 文件大?。?/td> | 168K |
| 代理商： | AND8020D |
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AND8020/D
http://onsemi.com
8
Internal 100 Termination (LVDS)
For some technologies, such as LVDS, this passive 100
internal termination can provide sufficient termination for the
driver as shown in Figure 10. Devices with a Combo Pin will
require this pin to remain open, while devices with singulated
internal resistors require the two pinned out V
t
nodes for a
differential pair to be shorted together to provide the 100
termination.
Figure 10. LVDS Interconnect with Internal
Termination
Open V
t
Pin
R
R
(*or twisted pair)
LVDS Driver
Receiver
*TLine Z
0
*TLine Z
0
Internal Termination Combo Pin
Internal Termination Singulated Pins
R
R
(*or twisted pair)
LVDS Driver
Receiver
*TLine Z
0
*TLine Z
0
Vt1
Vt2
Shorted
Differential ECL outputs can be terminated as independent
complimentary singleended lines. Both sides of any
differential pair must be terminated as identically as possible
to minimize phase error and pulse width duty cycle skew.
The I
OH
currents in these two cases will vary the DC V
OH
levels by
40 mV. However in the vast majority of cases, DC
levels are well centered in their specification windows, thus
this variation will simply move the level within the valid
specification window and no loss of worst case noise margin
will be seen.
The I
OL
situation on the other hand does pose a potential
AC problem. In the worst Case #1 I
OLmin
situation, the
output emitter follower could move into the cutoff state
(0 mA). The output emitter followers of ECL devices are
designed to be in the conducting, active region of operation
at all times. When forced into cutoff, the delay of the device
will be increased due to the extra time required to pull the
output emitter follower out of the cutoff state. Again, this
situation will arise only under a number of simultaneous
worst case situations and therefore, is highly unlikely to
occur. But, because of the potential, it should not be
overlooked.
Output Drive Characteristics
Figure 11 shows the nominal output characteristics for
ECL devices operating in negative ECL mode, driving
various load impedances (including the standard 50
returned to a negative two volt supply. The output
resistances, RH (high state output resistance) and RL (low
state output resistance), are obtained from the reciprocal of
the slope at the desired operating point. Many applications
require loads other than 50 the resulting V
OH
and V
OL
levels can be estimated using the following technique.
)
V
OH
2.0
0
5
10
15
0.75
1.0
1.25
20
25
30
35
40
1.75
0.5 0.25
0
OUTPUT VOLTAGE (V)
O
SLOPE = 6 8
1.5
Figure 11. Normal Output Levels Driving Various
Load Impedances
V
OL
T
A
=25
°
C
25
to 2.0 V
50
to 2.0 V
150
to 2.0 V
100
to 2.0 V
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