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參數(shù)資料
| 型號： | AND8020D |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Termination of ECL Logic Devices with EF (Emitter Follower) OUTPUT Structure |
| 中文描述： | ECL邏輯器件的終止與英法（發(fā)射極跟隨器）輸出結(jié)構(gòu) |
| 文件頁數(shù)： | 12/18頁 |
| 文件大?。?/td> | 168K |
| 代理商： | AND8020D |
AND8020/D
http://onsemi.com
12
From this relationship, V
A
= V
O
/ 2, an incident wave
of half amplitude propagates down the transmission line. At
the Receivers input Point B, typically high impedance, the
transmission line sees an unterminated open line and the
signal reflection coefficient at the Receiver load is
approximately unity. The reflection causes the voltage to
double at the receiving end. When the reflected wave arrives
back at the source end, its energy is dissipated by the series
resistor. When the sum of the source and series impedance
is equal to the characteristic impedance of the line, no further
reflections occur.
Calculation of R
t
The Emitter PullDown Resistor, R
t
, functions to
establish V
OH
and V
OL
levels. Voltage transitions imposed
on R
t
propagate through R
S
and Z
0
to a receiver. Negative
voltage transition are current limited by R
t
, R
S
, and Z
0
when
the driver output switches to the low state. The R
t
value must
maximize the negative voltage transition and prevent the
output transistor from entering the cutoff operating region in
a low state (Figure 15).
*TLine Z
0
V
EE
R
S
Receiver
Figure 15. Equivalent Circuit for RE Determination
Driver
R
O
R
t
The worst case scenario occurs when the driver output
emitter follower enters into cutoff during a negative going
transition. When this happens, the driver can be considered
opened and, at the instant it opens, the line characteristic
impedance behaves as a linear resistor returned to V
OH
. The
model becomes a simple series resistive network as shown
in Figure 16.
*TLine Z
0
V
EE
R
S
Figure 16. Equivalent Circuit with Output Cutoff
V
EE
V
OH
R
t
The maximum current, I
max
, occurs at the instant the
switch opens and is calculated by:
( VOH
( Rt
Imax
VEE)
Z0)
RS
(eq. 31)
An initial current, I
init
,
must be sufficient to generate a
transient voltage equal to half of the logic swing since the
voltage at the receiver will double due the reflection
coefficient approaching 1.0 for series termination. To
accommodate reflections caused by discontinuities and load
capacitances the transient voltage should be increased by
25%. Thus, I
init
is defined as:
Iinit
1.25 *
Vpp
2
Z0
(eq. 32)
To satisfy the initial constraints of I
max
> I
init
:
( VOH
( Rt
VEE)
Z0)
RS
1.25 *
VSWING
Z0
2
(eq. 33)
Solving for R
t
, gives the inequality:
Rt
( KZ0) Z0
RS
(eq. 34)
Where:
Z
0
= Line Characteristic Impedance
R
O
= Output Impedance of the Driver Gate
R
S
= Termination Resistance
KZ
0
= Coefficient to Z
0
For various series, the coefficient to Z
0
, KZ
0
, is presented
in Table E: Coefficient to Z
0
.
Table E. Coefficient to Z
0
Series
KZ
0
4.0
10EP
100LVEL
4.01
10EL
5.99
10E
7.10
100E
6.57
For the 10EP series (LVPECL mode operation),
where V
OH
= 2.4 V, V
SWING
= 0.8 V, and V
EE
= 0.0 V:
(2.4
0.0)
(Rt
RS
Z0)
0.5
Z0
* Z0
RS
Rt
4.0
(eq. 35)
For the 100LVEL series (LVPECL mode operation),
where: V
OH
= 2.345 V, V
SWING
= 0.750 V, V
EE
= 0.0 V:
(2.345
0.0)
(Rt
RS
Z0)
0.468
Z0
* Z0
RS
Rt
4.01
(eq. 36)
For the 10EL series (PECL mode operation),
where: V
OH
= 4.185 V, V
SWING
= 0.958 V, V
EE
= 0.0 V:
(4.185
0.0)
(Rt
RS
Z0)
0.599
Z0
* Z0
RS
Rt
5.99
(eq. 37)
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