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參數(shù)資料
| 型號： | AND8020D |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Termination of ECL Logic Devices with EF (Emitter Follower) OUTPUT Structure |
| 中文描述： | ECL邏輯器件的終止與英法（發(fā)射極跟隨器）輸出結構 |
| 文件頁數(shù)： | 2/18頁 |
| 文件大?。?/td> | 168K |
| 代理商： | AND8020D |
AND8020/D
http://onsemi.com
2
INTRODUCTION
Static DC Termination Analysis
A standard Emitter Coupled Logic (ECL) output driver
typically uses a current switching differential with an emitter
follower for level shifting the output and the internal CML
levels to familiar ECL levels. This output driver architecture
presents about 68
internal impedance in both LOW and
HIGH states when properly current biased. This results in a
typical V
PP
signal of 800 mV
PP
(measured singleendedly on
each line) swinging around a DC voltage point of
V
CC
1.3 V when properly terminated and operating
correctly as shown in Figure 1.
Q
V
EE
Driver
V
CC
D
V
CC
V
EE
Receiver
8 Internal Output
Impedance
V
EE
Figure 1. Typical ECL Output with Emitter Follower Output Structure,
Typical Termination, and Typical ECL Input Interconnect
Q
D
R
E
R
E
For proper static and dynamic operation, the output
emitter follower transistor must remain in the active region
of operation which requires an external resistive path be
provided from the output pin to a voltage more negative than
worst case V
OL
, such as V
EE
. The resistor, R
E
, is considered
a current bias for the Emitter Follower output structure.
When properly terminated and current biased (loaded),
the outputs will generate both: (1) static state voltage levels
V
OL
(LOW) or V
OH
(HIGH) and (2) a dynamic transition
edge (tr or tf) between state levels.
Static State Voltage Levels
Figure 2 illustrates the typical relationship of static signal
levels and dynamic transition edges between an Output
Driver Signal and a Receiver Input Signal. Both outputs of
a differential driver should always be terminated and loaded
as identically as possible to preserve minimum skew and
jitter operation of the device.
V
IH
V
OH
V
IL
V
CC
V
OL
V
EE
Figure 2. State Levels V
OH
, V
OL
,
and Dynamic Transitions at Q or Q and D or D
V
CC
1.3 V
tr
tf
V
IH
V
OH
V
IL
V
CC
V
OL
V
EE
V
CC
1.3 V
tr
tf
Output
Driver
Signal
Input
Receiver
Signal
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