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| 型號： | AND8020D |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Termination of ECL Logic Devices with EF (Emitter Follower) OUTPUT Structure |
| 中文描述： | ECL邏輯器件的終止與英法（發(fā)射極跟隨器）輸出結構 |
| 文件頁數(shù)： | 18/18頁 |
| 文件大?。?/td> | 168K |
| 代理商： | AND8020D |
AND8020/D
http://onsemi.com
18
Combining the high impedance and impedance matching
networks results in an input voltage scheme shown in
Figure 24. This creates the proper input voltage , VBIAS,
using fewer components.
V
TT
V
CC
Figure 24. VBIAS and AutoOscillation Suppression
with Thevenin Parallel Network
R1
Receiver
OUT
OUTb
IN
R
t
R
t
V
EE
0.001 F
R
Z
R2
INb
0.001 F
For a 3.3 V V
CC
, the values of R1 and R2 provide a
Thevenin parallel network divider voltage with V
IH
in the
V
IHCMR
of the receiver. Current through the divider
develops the default offset across R
z
and can be adjusted as
needed. For example, in Z
0
= 50 traces, a 30 mV default
offset difference will be created if V
CC
= 3.3 V and the DC
bias voltage is 2.0 V (typical V
BB
) when:
R1
4.22 k
R2
6.34 k
RZ
100
The 0.001 coupling cap may need to be adjusted to
frequency and Vpp amplitude of the receiver input signal.
A similar singleended network may be used with only
one coupling cap and sufficient bypass capacitance on the
nondriven resistor to preserve a DC level.
Output Level Shifting
Receiver inputs may be level shifted using capacitive
coupling and adjusting VBIAS within the acceptable
common mode range for V
IH
. Output levels may also be
changed independent of input levels. The driver device may
be operated with both V
CC
and V
EE
at shifted values. This
is used at the factory to evaluate devices and conveniently
port signals directly into standard 50
equipment modules. The V
CC
is fixed to +2.0 V above Test
System chassis ground and the test equipment internal 50
impedance constitutes a proper signal termination. Thus, the
split V
EE
supply is adjusted to a negative value.
impedance
|V
CC
V
EE
|
3.0
Split V
CC
+2.0
Split V
EE
1.0
Unit
V
3.3
+2.0
1.3
V
5.0
+2.0
3.0
V
5.5
+2.0
3.5
V
Output levels may be shifted to symmetrically cross 0.0 V
by a similar method although the advantage of conveniently
directly connecting into standard test equipment is no longer
available.
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AND8020/D
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