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參數(shù)資料
| 型號： | AND8020D |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Termination of ECL Logic Devices with EF (Emitter Follower) OUTPUT Structure |
| 中文描述： | ECL邏輯器件的終止與英法（發(fā)射極跟隨器）輸出結構 |
| 文件頁數(shù)： | 4/18頁 |
| 文件大?。?/td> | 168K |
| 代理商： | AND8020D |
AND8020/D
http://onsemi.com
4
SECTION 1. UNTERMINATED LINES
R
From transmission line theory, when the driver R
E
develops a V swing, the signal propagates from point A
arriving at point B at time Td later as shown in Figure 3. This
configuration is also referred to as a stub or an open line.
Figure 3. Unterminated Transmission Line Stub
V
EE
TLine Z
0
A
B
Td
R
E
At point B, the signal is reflected as a function of
L
. If the
input impedance of the receiving gate is large relative to the
line characteristic impedance, according to Equation 4:
(RL
(RL
Where:
L
= Load Reflection Coefficient
R
L
= Load Impedance
Z
0
= Line Characteristic Impedance
A large positive reflection occurs resulting in overshoot.
The reflected signal reaches point A at time 2Td , and a large
negative reflection results because the output impedance of
the driver gate is much less than the line characteristic
impedance (i.e. R
O
<< Z
0
).
When the reflected signal arrives at the source it is
reflected back toward the load with a magnitude dictated by
the source reflection coefficient:
(Rs
(Rs
Where:
S
= Source Reflection Coefficient
R
L
= Source Impedance
Z
0
= Line Characteristic Impedance
The reflected signal continues to be reflected by the source
and load impedances and is attenuated with each passage over
the transmission line. The output response appears as a
damped oscillation asymptotically approaching a steady state
value. This phenomena is often referred to as “ringing.”
The importance of minimizing the reflected signals lies in
their adverse affect on noise margin and the potential for
driving the input transistors of the succeeding stage into
saturation. Both of these phenomena can lead to less than
ideal system performance. To maximize signal integrity on
transmission lines, four basic techniques are available:
1. Minimizing Interconnect Line Lengths (Section 1)
2. Parallel Termination (Sections 2 and 3)
3. Series Termination (Section 4)
4. Diode Termination (Section 5)
L
Z0)
Z0)
(eq. 4)
S
Z0)
Z0)
(eq. 5)
Interconnect Line Lengths
The output signal Waveform rise (tr) and fall (tf) time are
measured from the 20% and 80% levels of the static signal
levels. This edge rate represents the waveforms highest
harmonic and determines the maximum unterminated open
line trace length, L
max
, permissible without sustaining
signal reflections.
The impetus in restricting interconnect lengths, L, is to
mitigate the effects of overshoot and undershoot. A handy
rule of thumb is that the undershoot can be limited to less
than 15% of the logic swing if the two way line delay is less
than the rise time of the pulse. With an undershoot of <15%,
the physics of the situation will result in an overshoot which
will not cause saturation problems at the receiving input.
Thus, the maximum line length can be determined:
Lmax
tr
2 * Tpd
(eq. 6)
Where:
L
max
= Maximum Open Line Length
t
r
= Signal Rise Time
T
pd
= Length Pulse Delay per Unit Length
Further, the propagation delay increases with gate
loading; thus, the effective delay per unit length (T
pdEff
) is
given as:
TpdEff
Tpd
1
CD
L * CO
(eq. 7)
Where:
T
pd
= Length Pulse Delay per Unit Length
C
D
= Distributed Capacitance
C
O
= Capacitance per Unit Length (Foot)
L = Line Length
Using the effective delay per unit length, Tpd
Eff,
yields:
tr
(2) (L) (Tpd)
1
CD
L * CO
(eq. 8)
Solving for L
max
line length produces:
Lmax
0.5
CD
CO
2
tr
tpd
2
CD
CO
(eq. 9)
Where:
L
max
= Line Length Maximum
C
D
= Distributed Capacitance
C
O
= Capacitance per Unit Length (Foot)
T
pd
= Length Pulse Delay per Unit Length
Assuming a worst case capacitance of 2 pF and a rise time
of 100 ps for EP gives a value of 0.03 inch for the maximum
open line length. Maximum open line lengths derived from
SPICE simulations for single and double gate loads, a
maximum overshoot of 40% and undershoot of 20% was
assumed. The simulation results indicate that for a 50
a stub length of
0.03 inches will limit the overshoot to less
than 40%, and the undershoot to within 20% of the logic
swing. Signal traces will most assuredly be larger than
0.03 inch for most practical applications.
Therefore, it will be necessary to use controlled
impedance environments for EP devices in general and
devices with faster edges.
line,
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