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參數(shù)資料
| 型號： | AND8020 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Termination of ECL Logic Devices with EF (Emitter Follower) OUTPUT Structure |
| 中文描述： | ECL邏輯器件的終止與英法（發(fā)射極跟隨器）輸出結(jié)構(gòu) |
| 文件頁數(shù)： | 17/18頁 |
| 文件大?。?/td> | 168K |
| 代理商： | AND8020 |
AND8020/D
http://onsemi.com
17
When the coupling capacitor is physically located near
enough to the receiver input pins to prohibit reflections on the
connecting trace length or signal impedance matching has
been accomplished prior to cap coupling, then a simple high
value resistor divider network from V
CC
to V
EE
is
recommended as shown in Figure 23. Differential and
SingleEnded AC Configurations Using NonV
BB
Biasing
(A and B). This network total resistance may be from 1 K
to 10 K . For 50 impedance traces, the typical value for the
voltage divider resistors are given in Table F. Typical Rebias
and Impedance Matching Resistor Network Values @
Z
0
= 50. Note the impedance presented to a signal is
5 K
Table F. Typical Rebias and Impedance Matching Resistor Network Values @ Z
0
= 50
Resistor
|V
CC
V
EE
| = 5.0 V
|V
CC
V
EE
| = 3.3 V
|V
CC
V
EE
| = 2.5 V
Units
R1 (R1
′
)
4
4
4
K
R2 (R2
′
)
6
6
6
K
V
rebias
3.3
2.2
1.7
V
When the coupling capacitor is physically located at a
distance from receiver over a trace or cable length capable
of sustaining reflections, a Thevenin parallel network
matching the line of impedance is recommended for their
suppression. This is shown in Figure 23. Differential and
SingleEnded AC Configurations Using NonV
BB
Biasing
(A and B). The rebias voltage may always be safely set at
V
CC
1.3. For 50
impedance traces, the typical value for
the voltage divider resistors are given in Table G. Typical
Rebias and Impedance Matching Resistor Network Values @
Z
0
= 50.
Table G. Typical Rebias and Impedance Matching Resistor Network Values @ Z
0
= 50
Resistor
|V
CC
V
EE
| = 5.0 V
|V
CC
V
EE
| = 3.3 V
|V
CC
V
EE
| = 2.5 V
Units
R1 (R1
′
)
68
83
96.15
R2 (R2
′
)
192
127
104.16
V
rebias
3.7
2.0
1.2
V
Figure 23. Differential and SingleEnded AC
Configurations Using NonV
BB
Biasing
V
CC
Receiver
OUT
OUTb
IN
INb
R
t
R
t
V
TT
0.001 F
0.001 F
V
EE
R2
R2
R1
R1
V
CC
Receiver
OUT
OUTb
IN
V
TT
0.001 F
V
EE
R2
R2
R1
R1
R
t
R
t
A. Differential
B. SingleEnded
The characterized V
BB
reference voltage bias, VBIAS, is
V
CC
1.33 V, but a device is not restricted to this VBIAS
value. The VBIAS range is determined by the Vpp
amplitude and the signal HIGH level, V
IH
. Input HIGH
level, V
IH
, is constrained by the data sheet specification of
common mode range, V
IHCMR
or V
CMR
. Thus, the VBIAS
range is constrained:
VBIASmax
VIHCMRmax
VBIASmin
VIHCMRmin
A singleended source into a differential type input signal
amplitude swing, V
pp
, is typically constrained from
V
ppmin
= 300 mV to V
ppmax
= 1000 mV.
An input signal must swing symmetrically above and
below VBIAS to preserve a 50% duty cycle out of the
receiver. Differential signals must have identical crosspoint
voltages to preserve minimum phase error and duty cycle
error. Crosspoint voltages are determined by the matched
precision of the resistor divider network from V
CC
to V
EE
.
( 0.5 ) ( Vpp )
( 0.5 ) ( Vpp )
AutoOscillation Suppression without V
BB
For a configuration without a V
BB
reference pin, such as
illustrated in Figure 23, the resistor network may be
modified to have an input voltage of 20 to 30 mV offset
between the input pins. Either a high resistor value divider
or a Thevenin parallel network may be modified to
accomplish this input voltage . This is accomplished by
altering the values of R1, R1
′
, R2, and R2
′
.
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