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參數(shù)資料
| 型號： | AND8020 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Termination of ECL Logic Devices with EF (Emitter Follower) OUTPUT Structure |
| 中文描述： | ECL邏輯器件的終止與英法（發(fā)射極跟隨器）輸出結構 |
| 文件頁數(shù)： | 10/18頁 |
| 文件大小： | 168K |
| 代理商： | AND8020 |
AND8020/D
http://onsemi.com
10
Because the resistor divider network of R1 and R2 is used
to generate V
TT
, the variation in V
TT
will be intimately tied
to the variation in V
CC
. Differentiating the equation for V
TT
with respect to V
CC
yields:
VTT
VCC
( R1
R2
R2 )
VCC
(eq. 24)
For the nominal case, this equation reduces to:
VTT
0.6
VCC
(eq. 25)
If V
CC
=
As mentioned previously, the real potential for problems
will be if the V
OL
level can potentially put the output emitter
follower out of the active operating region and into cutoff.
Because of the relationship between the V
CC
and V
TT
levels,
the only cutoff risk condition occurs at V
CCmin
, the lowest
value of V
CC
. Applying the equation for I
OLmin
under this
5% V
CC
condition yields:
( VOLmin
5% =
0.25 V, then V
TT
=
0.15 V.
IOLmin
VTT)
Rt
(eq. 26)
IOLmin
(4.75
1.85)
50
2.85
1.0 mA
(eq. 27)
The results of this cutoff risk analysis show there is no
potential for the output emitter follower to be in cutoff. This
would indicate a Thevenin equivalent termination scheme is
more robust to variation in V
CC
. Since the designer has the
flexibility of choosing the V
TT
level via the selection of the
R1 and R2 resistors, the following procedure can be used.
At 5% minimal variation case for V
CC
:
V
CC
= 4.75 V
V
TT
= V
CC
2.0 V = 2.75 V
R2 = 119
R1 = 86
Thus:
I
OHmax
= 23 mA
I
OLmin
= 3.0 mA
At +5% minimal variation case for V
CC
:
V
CC
= 5.25 V
V
TT
= 3.05 V
Thus:
I
OHmax
= 28 mA
I
OLmin
= 5.2 mA
Although the output currents are slightly higher than
nominal, the elimination of emitter follower cutoff risk is
well justified.
When the equivalent termination resistance matches the
line impedance, no reflection occurs because all the energy
in the signal is dissipated by the termination. Hence, in
comparing properly terminated schemes parallel and
Thevenin, a primary consideration is the power supply
requirements. As mentioned earlier, the parallel V
TT
scheme
requires an extra power supply; however, the Thevenin
termination dissipates 10 times more DC power.
Fortunately, this extra power dissipation cannot be seen on
the die; therefore, either technique results in similar die
junction temperatures.
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