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參數(shù)資料
| 型號(hào)： | AM79C961AKIW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
| 中文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP132 |
| 封裝： | PLASTIC, QFP-132 |
| 文件頁(yè)數(shù)： | 92/206頁(yè) |
| 文件大?。?/td> | 1507K |
| 代理商： | AM79C961AKIW |
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Am79C961A
Abnormal network conditions include:
I
Loss of carrier
I
Late collision
I
SQE Test Error (Does not apply to 10BASE-T port.)
These should not occur on a correctly configured 802.3
network, and will be reported if they do.
When an error occurs in the middle of a multi-buffer
frame transmission, the error status will be written in
the current descriptor. The OWN bit(s) in the subse-
quent descriptor(s) will be reset until the STP (the next
frame) is found.
Loss of Carrier
A loss of carrier condition will be reported if the PC-
net-ISA II controller cannot observe receive activity
while it is transmitting on the AUI port. After the PC-
net-ISA II controller initiates a transmission, it will ex-
pect to see data
“
looped back
”
on the DI
±
pair. This will
internally generate a
“
carrier sense,
”
indicating that the
integrity of the data path to and from the MAU is intact,
and that the MAU is operating correctly. This
“
carrier
sense
”
signal must be asserted before the end of the
transmission. If
“
carrier sense
”
does not become active
in response to the data transmission, or becomes inac-
tive before the end of transmission, the loss of carrier
(LCAR) error bit will be set in TMD2 after the frame has
been transmitted. The frame will not be re-tried on the
basis of an LCAR error. In 10BASE-T mode LCAR will
indicate that Jabber or Link Fail state has occurred.
Late Collision
A late collision will be reported if a collision condition
occurs after one slot time (512 bit times) after the trans-
mit process was initiated (first bit of preamble com-
menced). The PCnet-ISA II controller will abandon the
transmit process for the particular frame, set Late Col-
lision (LCOL) in the associated TMD3, and process the
next transmit frame in the ring. Frames experiencing a
late collision will not be re-tried. Recovery from this
condition must be performed by upper-layer software.
SQE Test Error
During the inter packet gap time following the comple-
tion of a transmitted message, the AUI CI
±
pair is
asserted by some transceivers as a self-test. The inte-
gral Manchester Encoder/Decoder will expect the SQE
Test Message (nominal 10 MHz sequence) to be
returned via the CI
±
pair within a 40 network bit time
period after DI
±
pair goes inactive. If the CI
±
inputs are
not asserted within the 40 network bit time period fol-
lowing the completion of transmission, then the PC-
net-ISA II controller will set the CERR bit in CSR0.
CERR will be asserted in 10BASE-T mode after trans-
mit if T-MAU is in Link Fail state. CERR will never cause
INTR to be activated. It will, however, set the ERR bit in
CSR0.
Host related transmit exception conditions include
BUFF and UFLO as described in the Transmit Descrip-
tor section.
Receive Operation
The receive operation and features of the PCnet-ISA II
controller are controlled by programmable options.
Receive Function Programming
Automatic pad field stripping is enabled by setting the
ASTRP_RCV bit in CSR4; this can provide flexibility in
the reception of messages using the 802.3 frame format.
All receive frames can be accepted by setting the
PROM bit in CSR15. When PROM is set, the PC-
net-ISA II controller will attempt to receive all mes-
sages, subject to minimum frame enforcement.
Promiscuous mode overrides the effect of the Disable
Receive Broadcast bit on receiving broadcast frames.
The point at which the BMU will start to transfer data
from the receive FIFO to buffer memory is controlled by
the RCVFW bits in CSR80. The default established
during reset is 10b, which sets the threshold flag at 64
bytes empty.
Automatic Pad Stripping
During reception of an 802.3 frame the pad field can be
stripped automatically. ASTRP_RCV (bit 10 in CSR4) =
1 enables the automatic pad stripping feature. The pad
field will be stripped before the frame is passed to the
FIFO, thus preserving FIFO space for additional
frames. The FCS field will also be stripped, since it is
computed at the transmitting station based on the data
and pad field characters, and will be invalid for a
receive frame that has had the pad characters stripped.
The number of bytes to be stripped is calculated from
the embedded length field (as defined in the IEEE
802.3 definition) contained in the frame. The length
indicates the actual number of LLC data bytes con-
tained in the message. Any received frame which con-
tains a length field less than 46 bytes will have the pad
field stripped (if ASTRP_RCV is set). Receive frames
which have a length field of 46 bytes or greater will be
passed to the host unmodified.
Since any valid Ethernet Type field value will always be
greater than a normal 802.3 Length field (
≥
46), the PC-
net-ISA II controller will not attempt to strip valid Ether-
net frames.
Note that for some network protocols the value passed
in the Ethernet Type and/or 802.3 Length field is not
compliant with either standard and may cause problems.
The diagram below shows the byte/bit ordering of the
received length field for an 802.3 compatible frame
format.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C961APDLUTS | 制造商:Advanced Micro Devices 功能描述: |
| AM79C961AVC | 制造商:Rochester Electronics LLC 功能描述: 制造商:Advanced Micro Devices 功能描述:LAN Node Controller, 144 Pin, TQFP |
| AM79C961AVC/W | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller |
| AM79C961AVC\\W | 制造商:Rochester Electronics LLC 功能描述: |
| AM79C961AVC\W | 制造商:Rochester Electronics LLC 功能描述: |
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