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參數(shù)資料
| 型號： | AM79C961AKIW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
| 中文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP132 |
| 封裝： | PLASTIC, QFP-132 |
| 文件頁數(shù)： | 185/206頁 |
| 文件大?。?/td> | 1507K |
| 代理商： | AM79C961AKIW |
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APPENDIX B
Am79C961A
185
Layout Recommendations
for Reducing Noise
DECOUPLING LOW-PASS R/C
FILTER DESIGN
The PCnet-ISA II controller is an integrated, single-chip
Ethernet controller, which contains both digital and
analog circuitry. The analog circuitry contains a high
speed Phase-Locked Loop (PLL) and Voltage Con-
trolled Oscillator (VCO). Because of the mixed signal
characteristics of this chip, some extra precautions must
be taken into account when designing with this device.
Described in this section is a simple decoupling
low-pass R/C filter that can significantly increase noise
immunity of the PLL circuit, thus, prevent noise from
disrupting the VCO. Bit error rate, a common measure-
ment of network performance, as a result can be dras-
tically reduced. In certain cases the bit error rate can be
reduced by orders of magnitude.
Implementation of this filter is not necessary to achieve
a functional product that meets the IEEE 802.3 specifi-
cation and provides adequate performance. However,
this filter will help designers meet those specifications
with more margin.
Digital Decoupling
The DVSS pins that are sinking the most current are
those that provide the ground for the ISA bus output
signals since these outputs require 24 mA drivers.
The DVSS10 and DVSS12 pins provide the ground
for the internal digital logic. In addition, DVSS11
provides ground for the internal digital and for the
Input and I/O pins.
The CMOS technology used in fabricating the PC-
net-ISA II controller employs an n-type substrate. In this
technology, all V
DD
pins are electrically connected to
each other internally. Hence, in a four-layer board, when
decoupling between V
DD
and critical V
SS
pins, the spe-
cific V
DD
pin that you connect to is not critical. In fact, the
V
DD
connection of the decoupling capacitor can be
made directly to the power plane, near the closest V
DD
pin to the V
SS
pin of interest. However, we recommend
that the V
SS
connection of the decoupling capacitor be
made directly to the V
SS
pin of interest as shown.
AMD recommends that at least one low-frequency
bulk decoupling capacitor be used in the area of the
PCnet-ISA II controller. 22
μ
F capacitors have worked
well for this. In addition, a total of four or five 0.1
μ
F
capacitors have proven sufficient around the DV
SS
and DV
DD
pins that supply the drivers of the ISA bus
output pins.
Analog Decoupling
The most critical pins are the analog supply and ground
pins. All of the analog supply and ground pins are located
in one corner of the device. Specific requirements of the
analog supply pins are listed below.
AVSS1 and AVDD3
These pins provide the power and ground for the
Twisted Pair and AUI drivers. Hence, they are very
noisy. A dedicated 0.1
μ
F capacitor between these pins
is recommended.
AVSS2 and AVDD2
These pins are the most critical pins on the PCnet-ISA
II controller because they provide the power and
ground for the PLL portion of the chip. The VCO portion
of the PLL is sensitive to noise in the 60 kHz-200 kHz
range. To prevent noise in this frequency range from
disrupting the VCO, AMD strongly recommends that
the low-pass filter shown below be implemented on
these pins. Tests using this filter have shown signifi-
cantly increased noise immunity and reduced Bit Error
Rate (BER) statistics in designs using the PCnet-ISA II
controller.
V
DD
Pin
V
SS
Pin
PCnet-ISA II
via to V
DD
via to V
SS
plane
19364B-85
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