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參數(shù)資料
| 型號： | AM79C961AKIW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
| 中文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP132 |
| 封裝： | PLASTIC, QFP-132 |
| 文件頁數(shù)： | 80/206頁 |
| 文件大?。?/td> | 1507K |
| 代理商： | AM79C961AKIW |
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80
Am79C961A
EADI (External Address Detection
Interface)
This interface is provided to allow external address fil-
tering. It is selected by setting the EADISEL bit in
ISACSR2. This feature is typically utilized for terminal
servers, bridges and/or router type products. The use
of external logic is required to capture the serial bit
stream from the PCnet-ISA II controller, compare it with
a table of stored addresses or identifiers, and perform
the desired function.
The EADI interface operates directly from the NRZ
decoded data and clock recovered by the Manchester
decoder or input to the GPSI, allowing the external
address detection to be performed in parallel with
frame reception and address comparison in the MAC
Station Address Detection (SAD) block.
SRDCLK is provided to allow clocking of the receive bit
stream into the external address detection logic.
SRDCLK runs only during frame reception activity.
Once a received frame commences and data and clock
are available, the EADI logic will monitor the alternating
(
“
1,0") preamble pattern until the two ones of the Start
Frame Delimiter (
“
1,0,1,0,1,0,1,1") are detected, at
which point the SF/BD output will be driven HIGH.
After SF/BD is asserted the serial data from SRD
should be de-serialized and sent to a content address-
able memory (CAM) or other address detection device.
To allow simple serial to parallel conversion, SF/BD is
provided as a strobe and/or marker to indicate the
delineation of bytes, subsequent to the SFD. This pro-
vides a mechanism to allow not only capture and/or de-
coding of the physical or logical (group) address, it also
facilitates the capture of header information to
determine protocol and or inter-networking information.
The EAR pin is driven LOW by the external address
comparison logic to reject the frame.
If an internal address match is detected by comparison
with either the Physical or Logical Address field, the
frame will be accepted regardless of the condition of
EAR. Incoming frames which do not pass the internal
address comparison will continue to be received. This
allows approximately 58 byte times after the last desti-
nation address bit is available to generate the EAR
signal, assuming the device is not configured to accept
runt packets. EAR will be ignored after 64 byte times
after the SFD, and the frame will be accepted if EAR
has not been asserted before this time. If Runt Packet
Accept is configured, the EAR signal must be
generated prior to the receive message completion,
which could be as short as 12 byte times (assuming 6
bytes for source address, 2 bytes for length, no data, 4
bytes for FCS) after the last bit of the destination
address is available. EAR must have a pulse width of at
least 200 ns.
Note that setting the PROM bit (CSR15, bit 15) will
cause all receive frames to be received, regardless of
the state of the EAR input.
If the DRCUPA bit (CSR15.B) is set and the logical
address (LADRF) is set to zero, only frames which are
not rejected by EAR will be received.
The EADI interface will operate as long as the STRT bit
in CSR0 is set, even if the receiver and/or transmitter
are disabled by software (DTX and DRX bits in CSR15
set). This situation is useful as a power down mode in
that the PCnet-ISA II controller will not perform any
DMA operations; this saves power by not utilizing the
ISA bus driver circuits. However, external circuitry
could still respond to specific frames on the network to
facilitate remote node control.
The table below summarizes the operation of the EADI
features.
Internal/External Address Recognition Capabilities
General Purpose Serial Interface (GPSI)
The PCnet-ISA II controller contains a General
Purpose Serial Interface (GPSI) designed for testing
the digital portions of the chip. The MENDEC, AUI, and
twisted pair interface are by-passed once the device is
set up in the special
“
test mode
”
for accessing the GPSI
functions. Although this access is intended only for
testing the device, some users may find the non-en-
coded data functions useful in some special
applications. Note, however, that the GPSI functions
can be accessed only when the PCnet-ISA II devices
operate as a bus master.
The PCnet-ISA II GPSI signals are consistent with the
LANCE digital serial interface. Since the GPSI func-
tions can be accessed only through a special test
mode, expect some loss of functionality to the device
when the GPSI is invoked. The AUI and 10BASE-T
analog interfaces are disabled along with the internal
PROM
EAR
Required Timing
Received Messages
1
X
No timing requirements
All Received Frames
0
1
No timing requirements
All Received Frames
0
0
Low for 200 ns within 512 bits after SFD
Physical/Logical Matches
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C961APDLUTS | 制造商:Advanced Micro Devices 功能描述: |
| AM79C961AVC | 制造商:Rochester Electronics LLC 功能描述: 制造商:Advanced Micro Devices 功能描述:LAN Node Controller, 144 Pin, TQFP |
| AM79C961AVC/W | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller |
| AM79C961AVC\\W | 制造商:Rochester Electronics LLC 功能描述: |
| AM79C961AVC\W | 制造商:Rochester Electronics LLC 功能描述: |
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