- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366550 > AM79C961AKIW (ADVANCED MICRO DEVICES INC) PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA PDF資料下載
參數(shù)資料
| 型號(hào)： | AM79C961AKIW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
| 中文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP132 |
| 封裝： | PLASTIC, QFP-132 |
| 文件頁(yè)數(shù)： | 47/206頁(yè) |
| 文件大?。?/td> | 1507K |
| 代理商： | AM79C961AKIW |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)當(dāng)前第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)
Am79C961A
47
Bus Slave Mode
System Interface
The Bus Slave mode is the other fundamental operat-
ing mode available on the PCnet-ISA II controller.
Within the Bus Slave mode, the PCnet-ISA II can be
programmed for a Shared Memory or Programmed I/O
architecture. In the Bus Slave mode the PCnet-ISA II
controller uses the same descriptor and buffer architec-
ture as in the Bus Master mode, but these data struc-
tures are stored in a static RAM controlled by the
PCnet-ISA II controller. When operating with the
Shared Memory architecture, the local SRAM is visible
as a memory resource on the PC which can be
accessed through memory cycles on the ISA bus inter-
face. When operating with the Programmed I/O archi-
tecture, the local SRAM is accessible through I/O
cycles on the ISA bus. Specifically, the SRAM is acces-
sible using the RAP and IDP I/O ports to access the
ISACSR0 and ISACSR1 registers, which serve as the
SRAM Data port and SRAM Address Pointer port,
respectively.
In the Bus Slave mode, the PCnet-ISA II registers and
optional Ethernet physical address PROM look the
same and are accessed in the same way as in the Bus
Master mode.
The Boot PROM is selected by an external device
which drives the Boot PROM Address Match (BPAM)
input to the PCnet-ISA II controller. The PCnet-ISA II
controller can perform two 8-bit accesses from the 8-bit
Boot PROM and present 16-bits of data to accommo-
date 16 bit read accesses on the ISA bus.
When using the Shared Memory architecture mode,
access to the local SRAM works the same way as
access to the Boot PROM, with an external device gen-
erating the Shared Memory Address Match (SMAM)
signal and the PCnet-ISA II controller performing the
SRAM read or write and the 8/16 bit data conversion.
External logic must also drive MEMCS16 appropriately
for the 128Kbyte segment decoded from the LA[23:17]
signals.
The Programmed I/O architecture mode uses the RAP
and IDP ports to allow access to the local SRAM
hence, external address decoding is not necessary and
the SMAM pin is not used in Programmed I/O architec-
ture mode (SMAM should be tied HIGH in the Pro-
grammed I/O architecture mode). Similar to the Shared
Memory architecture mode, in the Programmed I/O ar-
chitecture mode, 8/16 bit conversion occurs when 16
bit reads and writes are performed on the SRAM Data
Port (ISACSR1).
Converting the local SRAM accesses from 8-bit cycles
to 16-bit cycles allows use of the much faster 16-bit
cycle timing while cutting the number of bus cycles in
half. This raises performance to more than 400% of
what could be achieved with 8-bit cycles. When the
Shared Memory architecture mode is used, converting
boot PROM accesses to 16-bit cycles allows the two
memory resources to be in the same 128 Kbyte block
of memory without a clash between two devices with
different data widths.
The PCnet-ISA II prefetches data from the SRAM to
allow fast, minimum wait-state read accesses of con-
secutive SRAM addresses. In both the Shared Memory
architecture and the Programmed I/O architecture,
prefetch data is read from a speculated address that
assumes that successive reads in time will be from
adjacent ascending addresses in the SRAM. At the
beginning of each SRAM read cycle, the PCnet-ISA II
determines whether the prefetched data can be
assumed to be valid. If the prefetched data can be
assumed to be valid, it is driven onto the ISA bus
without inserting any wait states. If the prefetched data
cannot be assumed to be valid, the PCnet-ISA II will in-
sert wait states into the ISA bus read cycle until the
correct word is read from the SRAM.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C961AVCW | PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
| AM79C961AVIW | PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
| Am79C965A | PCnet?-32 Single-Chip 32-Bit Ethernet Controller |
| AM79C970AKCW | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AKC | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C961APDLUTS | 制造商:Advanced Micro Devices 功能描述: |
| AM79C961AVC | 制造商:Rochester Electronics LLC 功能描述: 制造商:Advanced Micro Devices 功能描述:LAN Node Controller, 144 Pin, TQFP |
| AM79C961AVC/W | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller |
| AM79C961AVC\\W | 制造商:Rochester Electronics LLC 功能描述: |
| AM79C961AVC\W | 制造商:Rochester Electronics LLC 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。