參數(shù)資料
型號(hào)： AM79C32AJC
廠商： ADVANCED MICRO DEVICES INC
元件分類： 數(shù)字傳輸電路
英文描述： Digital Subscriber Controller⑩ (DSC⑩) Circuit
中文描述： DATACOM, DIGITAL SLIC, PQCC44
封裝： PLASTIC, LCC-44
文件頁(yè)數(shù)： 47/101頁(yè)
文件大小： 1607K
代理商： AM79C32AJC
Am79C30A/32A Data Sheet
47
D-Channel Error Register — (DER) — Read Only
The DER has the format illustrated in Table 48.
DER bits 0, 1, 3, 4, 5, and 6 are set when the last byte of the associated packet is read from the D-channel Receive
buffer.
The DER bits generate interrupts and are set/reset under the conditions shown in Table 49 (in addition to a hardware
reset).
Table 49.
DER Interrupts
Extended FIFO Control Register — (EFCR) — Read/Write
Address = Indirect 92H
Table 48.
D-Channel Error Register
Bit
Logical 1
Logical 0 (Default Value)
0
Received Packet Abort
No abort received
1
Non-integer number of bits have been received
Integer number of bits received
2
Collision Detected
No error
3
FCS Error
No error
4
Overflow Error
No error
5
Underflow Error
No error
6
Overrun Error
No error
7
Underrun Error
No error
Bit Generates Interrupt
0
Yes, if DMR2 bit 0 = 1 When seven consecutive 1s are received
within a packet (DSR1 bit 2 = 1)
1
Yes, if DMR2 bit 1 = 1 Upon error condition after closing flag has
been received
2
Yes, if DMR2 bit 2 = 1 See section on collision detection
Bit Set
Bit Reset
When the microprocessor reads the DER or
associated DRCR
When the microprocessor reads the DER or
associated DRCR
When the microprocessor reads the DER or when
DTCR is loaded
When the microprocessor reads the DER or
associated DRCR
When the microprocessor reads the DER or
associated DRCR
When the microprocessor reads the DER or
associated DRCR
When the microprocessor reads the DER or
associated DRCR
When the microprocessor reads the DER or when
DTCR is loaded
3
Yes, if DMR2 bit 3 = 1 If error occurs
4
Yes, if DMR2 bit 4 = 1 If error occurs
5
Yes, if DMR2 bit 5 = 1 If error occurs
6
Yes, if DMR2 bit 6 = 1 If error occurs
7
Yes, if DMR2 bit 7 = 1 If error occurs
Bit
Function
7
6
5
4
3
2
1
0
0
X
X
X
X
0
X
X
Bits 7 and 2 reserved, must be written to 0
See Table 20.
Bits 6–3 control attenuation of the analog sidetone path (ASTG)
0
X
X
X
X
0
0
X
Start of Second Received Packet In FIFO interrupt disabled
0
X
X
X
X
0
1
X
Start of Second Received Packet In FIFO interrupt enabled
0
X
X
X
X
0
X
0
Normal mode of FIFO operation
0
X
X
X
X
0
X
1
Extended mode of FIFO operation
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