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參數(shù)資料
| 型號(hào)： | AM79C32AJC |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | Digital Subscriber Controller⑩ (DSC⑩) Circuit |
| 中文描述： | DATACOM, DIGITAL SLIC, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁(yè)數(shù)： | 20/101頁(yè) |
| 文件大小： | 1607K |
| 代理商： | AM79C32AJC |
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20
Am79C30A/32A Data Sheet
The three D-channel loopback controls defined in
LMR2 bits 0, 1, and 2 are explained below:
Bit 0, D-channel loopback at Am79C30A/32A enable:
This remote loopback is provided for maintenance pur-
poses from the NT’s perspective. The NT transmits
D-channel bits to the Am79C30A/32A where they are
internally looped (with the Data Link Controller) and
transmitted back to the NT. The incoming D-channel
data can be accessed by the microprocessor; however,
the microprocessor cannot send data on the outgoing
D channel.
Any difference between the transmitted D-channel bits
and the received E-channel bits to/from the
Am79C30A/32A (normally detected as an error which
halts the transmission) is ignored, thereby allowing the
transmission to continue.
Bit 1, D-channel loopback at LIU enable:
This local loopback is provided for local testing. Data on
the incoming D channel is ignored. The data from the
microprocessor is processed by the DLC and then
looped back to the microprocessor.
Bit 2, D-channel back-off disable:
This loopback is provided for maintenance purposes
from the TE’s perspective. The Am79C30A/32A trans-
mits D-channel bits to the NT where they are looped
and transmitted back to the Am79C30A/32A in the E
channel. The operation is normal except differences
between the D and E channels do not halt the trans-
mission.
Multiframe Register (MF), Read/Write
Address = Indirect A6H
Am79C30A
NT/PABX
D
D
D
D
S
E
Am79C30A
NT/PABX
D
D
MPI
S
Am79C30A
NT/PABX
D
D
E
E
S
Table 14.
Multiframe Register
Bit
Logical 1
Logical 0 (Default Value)
0
Enable Multiframe sync
Disable Multiframe sync
1
Enable S-data available interrupt
Disable interrupt
2
Enable Q-bit buffer empty interrupt
Disable interrupt
3
Enable Multiframe change of state interrupt
Disable interrupt
4
First subframe
Not first subframe
5, 6
Not used, reads logical 0
Not used, reads logical 0
7
Multiframe synchronized (read only)
Multiframe not synchronized (read only)
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PDF描述 |
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| AM79C32AVC | Digital Subscriber Controller⑩ (DSC⑩) Circuit |
| AM79C850KC | SUPERNET-R 3 |
| AM79C850KCW | SUPERNET-R 3 |
| AM79C864AKC | Physical Layer Controller With Scrambler (PLC-S) |
| AM79C864AKCW | Physical Layer Controller With Scrambler (PLC-S) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C32AJC/D | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Advanced Micro Devices 功能描述: 制造商:AMD 功能描述: |
| AM79C32AJC/E | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AM79C32AJC/E4 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AM79C32AJCB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ISDN Line Interface |
| AM79C32APC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ISDN Line Interface |
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