參數資料
型號： AM79C32A
廠商： Advanced Micro Devices, Inc.
英文描述： Digital Subscriber Controller⑩ (DSC⑩) Circuit
中文描述： 數字用戶控制器⑩法（DSC⑩）電路
文件頁數： 17/101頁
文件大?。?/td> 1607K
代理商： AM79C32A
Am79C30A/32A Data Sheet
17
Transmission of Q bits
The microprocessor can load the Multiframe Q-bit
buffer (MFQB) once the Q-bit buffer empty bit (bit 6 of
the Multiframe S bit/Status buffer) is set. The Q-bit
buffer empty bit is set to a logical 1 at reset or when
data that has been written to the Multiframe Q-bit buffer
is transferred to the LIU. The Q-bit buffer empty bit is
cleared to a logical 0 when the Multiframe S-bit/Status
buffer is read. After multiframing has been requested
and established, the Am79C30A/32A transfers the data
written into the Q-bit Register to the LIU, synchronized
to the multiframe, irrespective of the receipt of valid
Q-control bits. If the microprocessor does not reload
the Q-bit Register for retransmissions, the Q-bit pattern
is repeated in the next multiframe.
If multiframing is enabled but multiframe synchroniza-
tion is not established, the LIU transmits the value
loaded in MFQB bit 4 in all Q bits. The default value of
MFQB bit 4 is a logical 0 which satisfies the CCITT rec-
ommendations. When synchronization is achieved, the
contents of MFQB bits 3 to 0 are transmitted according
to Table 8.
Loss of Multiframe Synchronization
The Am79C30A/32A continuously monitors the FA
(Q-bit control) and the M bits to ensure multiframe syn-
chronization. Once multiframe synchronization is es-
tablished, multiframe synchronization is lost if three
consecutive invalid multiframes are received, or the LIU
is no longer in state F6 or F7, or multiframing is dis-
abled. When loss of multiframe synchronization occurs,
bit 7 of the Multiframe Register is set to a logical 0, and
bit 7 of the Multiframe S bit/Status buffer is set to a
logical 1. The Am79C30A/32A also terminates the re-
ception of S bits and transmission of Q bits until multi-
framing synchronization is re-established.
HSW
The hookswitch circuitry on the DSC circuit provides the
attached microprocessor with a way of converting an
external mechanical hookswitch into a software status
condition capable of generating an interrupt. Debounce
and glitch rejection are provided internal to the DSC cir-
cuit. The logic rejects glitches less than 162 ns and pro-
vides debounce of 16 ms. HSW status reporting is
disabled after RESET. It is enabled by any of the follow-
ing: taking the device out of Idle mode, a write to a MUX
Control Register (MCR3–MCR1), or unmasking the
HSW interrupt.
Table 8.
Multiframing Structures
Frame Number
1
NT-to-TE Q Control Bit FA
1
NT-to-TE M Bit (M)
1
NT-to-TE S Bit (S)
SC11
TE-to-NT FA Bit (Q Bit)
Q1
2
3
0
0
0
0
SC21
SC31
0
0
4
5
0
0
0
0
SC41
SC51
0
0
6
7
8
1
0
0
0
0
0
SC12
SC22
SC32
Q2
0
0
9
10
0
0
0
0
SC42
SC52
0
0
11
12
1
0
0
0
SC13
SC23
Q3
0
13
14
0
0
0
0
SC33
SC43
0
0
15
16
0
1
0
0
SC53
SC14
0
Q4
17
18
0
0
0
0
SC24
SC34
0
0
19
20
1
0
0
1
0
0
1
SC44
SC54
SC11
0
0
Q1
2
0
0
SC21
0
etc.
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AM79C32AJC 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Digital Subscriber Controller⑩ (DSC⑩) Circuit
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