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參數(shù)資料
| 型號： | AM79C32A |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | Digital Subscriber Controller⑩ (DSC⑩) Circuit |
| 中文描述： | 數(shù)字用戶控制器⑩法（DSC⑩）電路 |
| 文件頁數(shù)： | 15/101頁 |
| 文件大?。?/td> | 1607K |
| 代理商： | AM79C32A |
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Am79C30A/32A Data Sheet
15
Line Interface Unit (LIU)
The LIU connects to the four-wire S Interface through a
pair of isolation transformers, one for the transmit and
one for the receive direction, as shown in Figure 1.
The receiver section of the LIU consists of a differential
receiver, circuitry for bit timing recovery, circuitry for de-
tecting High and Low marks, and a frame recovery cir-
cuit for frame synchronization. The receiver converts
the received pseudo-ternary coded signals to binary
before delivering them to the other blocks of the
Am79C30A/32A. It also performs collision detection (E-
and D-bit comparison) per the CCITT recommenda-
tions so several TEs can be connected to the same S
Interface.
The transmitter consists of a binary to pseudo-ternary
encoder and a differential line driver which meets the
CCITT recommendations for the S Interface.
The Am79C30A/32A can establish multiframe synchro-
nization, receive S bits, and transmit Q bits synchro-
nized to the received frame.
External Interface
The LIU can be connected to both point-to-point and
point-to-multipoint configurations at the CCITT S refer-
ence point. The point-to-point configuration consists of
one TE connected to the NT or PABX linecard. The
DLC
D-channel Mode Register 1
6
DMR1
R/W
86H
One byte transferred
DLC
D-channel Mode Register 2
7
DMR2
R/W
87H
One byte transferred
DLC
—
8
Perform 1–7
—
88H
4 bytes loaded 1–7
DLC
D-channel Receive Byte Count
Register
9
DRCR
R
89H
LSB, MSB
DLC
Random Number Generator
Register
10
RNGR1 (LSB)
R/W
8AH
One byte transferred
DLC
Random Number Generator
Register
11
RNGR2 (MSB)
R/W
8BH
One byte transferred
DLC
First Received Byte Address
Register 4
12
FRAR4
R/W
8CH
One byte transferred
DLC
Second Received Byte Address
Register 4
13
SRAR4
R/W
8DH
One byte transferred
DLC
D-channel Mode Register 3
14
DMR3
R/W
8EH
One byte transferred
DLC
D-channel Mode Register 4
15
DMR4
R/W
8FH
One byte transferred
DLC
—
16
Perform 12–15
—
90H
FRAR4, SRAR4, DMR3,
DMR4
DLC
Address Status Register
17
ASR
R
91H
One byte transferred
DLC
Extended FIFO Control Register
18
EFCR
R/W
92H
One byte transferred
PP
Peripheral Port Control Register 1
1
PPCR1
R/W
C0H
One byte transferred
PP
Peripheral Port Status Register
2
PPSR
R
C1H
One byte transferred
PP
Peripheral Port Interrupt Enable
Register
3
PPIER
R/W
C2H
One byte transferred
PP
Monitor Transmit Data Register
4
MTDR
W
C3H
One byte transferred
PP
Monitor Receive Data Register
5
MRDR
R
C3H
One byte transferred
PP
C/I Transmit Data Register 0
6
CITDR0
W
C4H
One byte transferred
PP
C/I Receive Data Register 0
7
CIRDR0
R
C4H
One byte transferred
PP
C/I Transmit Data Register 1
8
CITDR1
W
C5H
One byte transferred
PP
C/I Receive Data Register 1
9
CIRDR1
R
C5H
One byte transferred
PP
Peripheral Port Control Register 2
10
PPCR2
R/W
C8H
One byte transferred
PP
Peripheral Port Control Register 3
11
PPCR3
R/W
C9H
One byte transferred
Table 7.
Indirect Register Access Guide (Continued)
Operation
Block
Register
Register
Number
Indirect Name
Mode
Address
Byte Sequence
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