參數(shù)資料
型號(hào)： AM486DX2
廠商： Advanced Micro Devices, Inc.
英文描述： Am5X86⑩ Microprocessor Family
中文描述： Am5X86⑩微處理器家族
文件頁(yè)數(shù)： 35/67頁(yè)
文件大?。?/td> 1613K
代理商： AM486DX2
Am5
X
86 Microprocessor
35
AMD
PRELIMINARY
Data
from CPU
BRDY
BOFF
XX4
ADR
ADS
BLAST
M/IO
W/R
CLK
Figure 18. Burst Write with BOFF Assertion
CACHE
XX0
XX4
XX4
XX8
XXC
XX0
XX8
XXC
XX4
CACHE is asserted for cacheable reads, cacheable
code fetches, and write-backs/copy-backs. CACHE is
deasserted for non-cacheable reads, translation looka-
side buffer (TLB) replacements, locked cycles (except
for write-back cycles generated by an external snoop
operation that interrupts a locked read/modify/write se-
quence), I/O cycles, special cycles, and write-throughs.
CACHE is driven to its valid level in the same clock as
the assertion of ADS and remains valid until the next
RDY or BRDY assertion. The CACHE output pin floats
one clock after BOFF is asserted. Additionally, the signal
floats when HLDA is asserted.
The following steps describe the burst write sequence:
1.
The access is started by asserting: ADS = 0, M/IO
= 1, W/R = 1, CACHE = 0. The address offset always
is 0, so the burst write always starts on a cache line
boundary. CACHE transitions High (inactive) after
the first BRDY.
In the second clock cycle, BLAST is 1 to indicate
that the burst is not finished.
The burst write access is finished when BLAST is
0 and BRDY is 0.
When the RDY signal is returned instead of the BRDY
signal, the Am5
X
86 microprocessor halts the burst cycle
and proceeds with the standard non-burst cycle.
2.
3.
4.10.1 Locked Accesses
Locked accesses of an Am5
X
86 microprocessor occur
for read-modify-write operations and interrupt acknowl-
edge cycles. The timing is identical to the DX micropro-
cessor, although the state transitions differ from the
standard DX microprocessor. Unlike processor-initiated
accesses, state transitions for locked accesses are seen
by all processors in the system. Any locked read or write
generates an external bus cycle, regardless of cache
hit or miss. During locked cycles, the processor does
not recognize a HOLD request, but it does recognize
BOFF and AHOLD requests.
Locked read operations always read data from the ex-
ternal memory, regardless of whether the data is in the
cache. In the event that the data is in the cache and
unmodified, the cache line is invalidated and an external
read operation is performed. The data from the external
memory is used instead of the data in the cache, thus
ensuring that the locked read is seen by all other bus
masters. If a locked read occurs, the data is in the cache,
and it is modified. The microprocessor first copies back
the data to external memory, invalidates the cache line,
and then performs a read operation to the same location,
thus ensuring that the locked read is seen by all other
bus masters. At no time is the data in the cache used
directly by the microprocessor or a locked read opera-
tion before reading the data from external memory.
Since locked cycles always begin with a locked read
access, and locked read cycles always invalidate a
cache line, a locked write cycle to a valid cache line,
either modified or unmodified, does not occur.
4.10.2 Serialization
Locked accesses are totally serialized:
I
All reads and writes in the write buffer that precede
the locked access are issued on the bus before the
first locked access is executed.
I
No read or write after the last locked access is issued
internally or on the bus until the final RDY or BRDY
for all locked accesses.
I
It is possible to get a locked read, write-back, locked
write cycle.
相關(guān)PDF資料
PDF描述
AM486DX4 High-Performance, Clock-Selectable, 3.3 V, 32-Bit Microprocessor(3.3V高性能時(shí)鐘可選32位微處理器)
AM49DL320BGB701S 32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 32 Mbit (2M x 16-Bit) Pseudo Static RAM
AM49DL320BGB701T 32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 32 Mbit (2M x 16-Bit) Pseudo Static RAM
AM49DL320BGB851S 32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 32 Mbit (2M x 16-Bit) Pseudo Static RAM
AM49DL320BGB851T 32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 32 Mbit (2M x 16-Bit) Pseudo Static RAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM486DX2-66V16BGC 制造商:Advanced Micro Devices 功能描述:MPU AM486 RISC 32-Bit 0.35um 66MHz 5V 168-Pin PGA
AM486DX2-66V16BGI 制造商:Advanced Micro Devices 功能描述:MPU AM486 RISC 32-Bit 0.35um 66MHz 5V 168-Pin PGA
AM486DX2-66V16BHI 制造商:Advanced Micro Devices 功能描述:MPU AM486 RISC 32-Bit 0.35um 66MHz 5V 208-Pin SQFP
AM486DX4100C16BGI 制造商:AMD 功能描述:*
AM486DX5-133V16BHC 制造商:Advanced Micro Devices 功能描述:MPU AM486 RISC 32-Bit 0.35um 133MHz 5V 208-Pin SQFP
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