參數(shù)資料
型號(hào)： AM486DX2
廠(chǎng)商： Advanced Micro Devices, Inc.
英文描述： Am5X86⑩ Microprocessor Family
中文描述： Am5X86⑩微處理器家族
文件頁(yè)數(shù)： 20/67頁(yè)
文件大小： 1613K
代理商： AM486DX2
20
Am5
X
86 Microprocessor
AMD
PRELIMINARY
4.6
The cache line replacement algorithm uses the standard
Am486 CPU pseudo LRU (Least-Recently Used) strat-
egy. When a line must be placed in the internal cache,
the microprocessor first checks to see if there is an in-
valid line available in the set. If no invalid line is available,
the LRU algorithm replaces the least-recently used
cache line in the four-way set with the new cache line.
If the cache line for replacement is modified, the modi-
fied cache line is placed into the copy-back buffer for
copying back to external memory, and the new cache
line is placed into the cache. This copy-back ensures
that the external memory is updated with the modified
data upon replacement.
Cache Replacement Description
4.7
In computer systems, memory regions require specific
caching and memory write methods. For example, some
memory regions are non-cacheable while others are
cacheable but are write-through. To allow maximum
memory configuration, the microprocessor supports
specific memory region requirements. All bus masters,
such as DMA controllers, must reflect all data transfers
on the microprocessor local bus so that the micropro-
cessor can respond appropriately.
Memory Configuration
4.7.1
The Am5
X
86 CPU caches data based on the state of
the CD and NW bits in CR0, in conjunction with the KEN
signal, at the time of a burst read access from memory.
If the WB/WT signal is Low during the first BRDY, KEN
meets the standard setup and hold requirements and
the four 32-bit doublewords are still placed in the cache.
However, all cacheable accesses in this mode are con-
sidered write-through. When the WB/WT is High during
the first BRDY, the entire four 32-bit doubleword transfer
is considered write-back.
Cacheability
Note:
The CD bit in CR0 enables (0) or disables (1) the
internal cache. The NW bit in CR0 enables (0) or dis-
ables (1) write-through and snooping cycles. RESET
sets CD and NW o 1. Unlike RESET, however, SRESET
does not invalidate the cache nor does it modify the
values of CD and NW in CR0.
4.7.2
If the CPU is operating in Write-back mode (i.e., the
WB
WT pin was sampled High at RESET), the WB
WT
Write-Through/Write-Back
pin indicates whether an individual write access is exe-
cuted as write-through or write-back. The Am5
X
86 mi-
croprocessor does this on an access-by-access basis.
Once the cache line is in the cache, the STATUS bit is
tested each time the processor writes to the cache line
or a tag compare results in a hit during Bus-watching
mode. If the WB
WT signal is Low during the first BRDY
of the cache line read access, the cache line is consid-
ered a write-through access. Therefore, all writes to this
location in the cache are reflected on the external bus,
even if the cache line is write protected.
4.8
Cache Functionality in Write-Back
Mode
The description of cache functionality in Write-back
mode is divided into two sections: processor-initiated
cache functions and snooping actions.
4.8.1
Processor-Initiated Cache Functions and
State Transitions
The microprocessor contains two new buffers for use
with the MESI protocol support: the copy-back buffer
and the write-back buffer. The processor uses the copy-
back buffer for cache line replacement of modified lines.
The write-back buffer is used when an external bus mas-
ter hits a modified line in the cache during a snoop op-
eration and the cache line is designated for write-back
to main memory. Each buffer is four doublewords in size.
Figure 1 shows a diagram of the state transitions in-
duced by the local processor. When a read miss occurs,
the line selected for replacement remains in the modified
state until overwritten. A copy of the modified line is sent
to the copy-back buffer to be written back after replace-
ment. When reload has successfully completed, the line
is set either to the exclusive or the shared state, depend-
ing on the state of PWT and WB/WT signals.
Table 5. MESI Cache Line Status
Situation
Line valid Yes
External
memory
is...
Modified Exclusive
Yes
Shared
Yes
Invalid
No
out-of-
date
valid
valid
status
unknown
A write to
this cache
line...
does not
go to the
bus
does not go
to the bus
goes to
the bus
and
updates
goes
directly to
the bus
Invalid
Shared
Modified
Exclusive
Read_Hit
Read_Miss
(WB/WT = 1)
(PWT = 0)
Read_Miss
[(WB/WT = 0) + (PWT = 1)]
Write_Hit
Write_Hit + Read_Hit
Note:
Write_Hit
generates external
bus cycle.
Read_Hit
+ Write_Hit
Figure 1. Processor-Induced Line Transitions in
Write-Back Mode
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參數(shù)描述
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