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參數(shù)資料
| 型號： | AM486DX2 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | Am5X86⑩ Microprocessor Family |
| 中文描述： | Am5X86⑩微處理器家族 |
| 文件頁數(shù)： | 25/67頁 |
| 文件大?。?/td> | 1613K |
| 代理商： | AM486DX2 |
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Am5
X
86 Microprocessor
25
AMD
PRELIMINARY
4.8.3
The following scenarios describe the snooping actions
of an external bus master.
External Bus Master Snooping Actions
4.8.3.1
Scenario
: A snoop of the on-chip cache does not hit a
line, as shown in Figure 6.
Snoop Miss
Step 1 The microprocessor is placed in Snooping
mode with HOLD. HLDA must be High for a
minimum of one clock cycle before EADS as-
sertion. In the fastest case, this means that
HOLD was asserted one clock cycle before the
HLDA response.
Step 2 EADS and INV are applied to the microproces-
sor. If INV is 0, a read access caused the snoop-
ing cycle. If INV is 1, a write access caused the
snooping cycle.
Step 3 Two clock cycles after EADS is asserted, HITM
becomes valid. Because the addressed line is
not in the snooping cache, HITM is 1.
4.8.3.2
Scenario
: The snoop of the on-chip cache hits a line,
and the line is not modified (see Figure 7).
Snoop Hit to a Non-Modified Line
Step 1 The microprocessor is placed in Snooping
mode with HOLD. HLDA must be High for a
minimum of one clock cycle before EADS as-
sertion. In the fastest case, this means that
HOLD was asserted one clock cycle before the
HLDA response.
Step 2 EADS and INV are applied to the microproces-
sor. If INV is 0, a read access caused the snoop-
ing cycle. If INV is 1, a write access caused the
snooping cycle.
Step 3 Two clock cycles after EADS is asserted, HITM
becomes valid. In this case, HITM is 1.
4.8.4
Scenario
: Write-back accesses are always burst writes
with a length of four 32-bit words. For burst writes, the
burst always starts with the microprocessor line offset
at 0. HOLD must be deasserted before the write-back
can be performed (see Figure 8).
Write-Back Case
Step 1 HOLD places the microprocessor in Snooping
mode. HLDA must be High for a minimum of
one clock cycle before EADS assertion. In the
fastest case, this means that HOLD asserts one
clock cycle before the HLDA response.
Step 2 EADS and INV are asserted. If INV is 0, snoop-
ing is caused by a read access. If INV is 1,
snooping is caused by a write access. EADS is
not sampled again until after the modified line
is written back to memory. It is detected again
as early as in Step 11.
EADS
External
bus master’s
BOFF signal
Note:
The circled numbers in this figure represent the steps in section 4.8.4.
HLDA
Data
HOLD
HITM
ADS
INV
BRDY
BLAST
W/R
M/IO
CACHE
ADR
CLK
valid
n
n
n
n+4
n+8 n+12
n+1
valid
n
Figure 8. Snoop That Hits a Modified Line (Write-Back)
2
3
1
7
8
9
10
6
5
11
floating/tri-stated
floating/tri-stated
4
n+8
n+4
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM486DX4 | High-Performance, Clock-Selectable, 3.3 V, 32-Bit Microprocessor(3.3V高性能時鐘可選32位微處理器) |
| AM49DL320BGB701S | 32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 32 Mbit (2M x 16-Bit) Pseudo Static RAM |
| AM49DL320BGB701T | 32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 32 Mbit (2M x 16-Bit) Pseudo Static RAM |
| AM49DL320BGB851S | 32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 32 Mbit (2M x 16-Bit) Pseudo Static RAM |
| AM49DL320BGB851T | 32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 32 Mbit (2M x 16-Bit) Pseudo Static RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM486DX2-66V16BGC | 制造商:Advanced Micro Devices 功能描述:MPU AM486 RISC 32-Bit 0.35um 66MHz 5V 168-Pin PGA |
| AM486DX2-66V16BGI | 制造商:Advanced Micro Devices 功能描述:MPU AM486 RISC 32-Bit 0.35um 66MHz 5V 168-Pin PGA |
| AM486DX2-66V16BHI | 制造商:Advanced Micro Devices 功能描述:MPU AM486 RISC 32-Bit 0.35um 66MHz 5V 208-Pin SQFP |
| AM486DX4100C16BGI | 制造商:AMD 功能描述:* |
| AM486DX5-133V16BHC | 制造商:Advanced Micro Devices 功能描述:MPU AM486 RISC 32-Bit 0.35um 133MHz 5V 208-Pin SQFP |
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