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參數(shù)資料
| 型號： | AM486DX2 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | Am5X86⑩ Microprocessor Family |
| 中文描述： | Am5X86⑩微處理器家族 |
| 文件頁數(shù)： | 34/67頁 |
| 文件大?。?/td> | 1613K |
| 代理商： | AM486DX2 |
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34
Am5
X
86 Microprocessor
AMD
PRELIMINARY
4.9.3
As with snooping during normal operation, snooping is
permitted during a cache flush, whether initiated by the
FLUSH pin or WBINVD instruction. After completion of
the snoop, and write-back, if needed, the microproces-
sor completes the copy-back of modified cache lines.
Snooping During Cache Flushing
4.10 Burst Write
The Am5
X
86 microprocessor improves system perfor-
mance by implementing a burst write feature for cache
line write-backs and copy-backs. Standard write oper-
ations are still supported. Burst writes are always four
32-bit words and start at the beginning of a cache line
address of 0 for the starting access. The timing of the
BLAST and BRDY signals is identical to the burst read.
Figure 16 shows a burst write access. (See Figure 17
and Figure 18 for burst read and burst write access with
BOFF asserted.) In addition to using BLAST, the
CACHE signal indicates burstable cycles.
CACHE is a cycle definition pin used when in Write-back
mode (CACHE floats in Write-through mode). For pro-
cessor-initiated cycles, the signal indicates:
I
For a read cycle, the internal cacheability of the cycle
I
For a write cycle, a burst write-back or copy-back, if
KEN is asserted (for linefills).
Table 8. FLUSH Special Bus Cycles
A32–A2
M/IO D/C W/R BE3 BE2 BE1 BE0 Bus Cycle
0000 0001h
0
0
1
0
1
1
1
First Flush
Acknowledge
Second
Flush
Acknowledge
0000 0001h
0
0
1
1
1
0
1
W/R
BRDY
ADS
BLAST
ADR
M/IO
XX4
Data
XX0
XX0
XX4
XX8
XXC
Figure 16. Burst Write
CLK
CACHE
XXC
XX8
Data
to CPU
BRDY
BOFF
XX0
XX4
don’t care
ADR
XX0
ADS
BLAST
M/IO
W/R
CLK
XX4
XX4
XX8
XXC
XX4
XX8
XXC
Figure 17. Burst Read with BOFF Assertion
CACHE
相關PDF資料 |
PDF描述 |
|---|---|
| AM486DX4 | High-Performance, Clock-Selectable, 3.3 V, 32-Bit Microprocessor(3.3V高性能時鐘可選32位微處理器) |
| AM49DL320BGB701S | 32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 32 Mbit (2M x 16-Bit) Pseudo Static RAM |
| AM49DL320BGB701T | 32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 32 Mbit (2M x 16-Bit) Pseudo Static RAM |
| AM49DL320BGB851S | 32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 32 Mbit (2M x 16-Bit) Pseudo Static RAM |
| AM49DL320BGB851T | 32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 32 Mbit (2M x 16-Bit) Pseudo Static RAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AM486DX2-66V16BGC | 制造商:Advanced Micro Devices 功能描述:MPU AM486 RISC 32-Bit 0.35um 66MHz 5V 168-Pin PGA |
| AM486DX2-66V16BGI | 制造商:Advanced Micro Devices 功能描述:MPU AM486 RISC 32-Bit 0.35um 66MHz 5V 168-Pin PGA |
| AM486DX2-66V16BHI | 制造商:Advanced Micro Devices 功能描述:MPU AM486 RISC 32-Bit 0.35um 66MHz 5V 208-Pin SQFP |
| AM486DX4100C16BGI | 制造商:AMD 功能描述:* |
| AM486DX5-133V16BHC | 制造商:Advanced Micro Devices 功能描述:MPU AM486 RISC 32-Bit 0.35um 133MHz 5V 208-Pin SQFP |
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