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參數(shù)資料
| 型號(hào)： | AM45DL3208G |
| 廠商： | Advanced Micro Devices, Inc. |
| 元件分類： | SRAM |
| 英文描述： | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM |
| 中文描述： | 堆疊式多芯片封裝（MCP）閃存和SRAM |
| 文件頁(yè)數(shù)： | 57/66頁(yè) |
| 文件大小： | 1196K |
| 代理商： | AM45DL3208G |
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March 12, 2004
Am45DL3208G
55
P R E L I M I N A R Y
Pseudo SRAM AC CHARACTERISTICS
Power Up Time
When powering up the SRAM, maintain V
CC
s for 100 μs minimum with CE#1s at V
IH
.
Read Cycle
Notes:
1. CE1#s = OE# = V
IL
, CE2s = WE# = V
IH
, UB#s and/or LB#s = V
IL
2. Do not access device with cycle timing shorter than t
RC
for continuous periods < 10 μs.
Figure 29.
Pseudo SRAM Read Cycle—Address Controlled
Parameter
Symbol
Description
Speed
Unit
70
85
t
RC
Read Cycle Time
Min
70
85
ns
t
AA
Address Access Time
Max
70
85
ns
t
CO1
, t
CO2
Chip Enable to Output
Max
70
85
ns
t
OE
Output Enable Access Time
Max
35
40
ns
t
BA
LB#s, UB#s to Access Time
Max
70
85
ns
t
LZ1
, t
LZ2
Chip Enable (CE1#s Low and CE2s High) to Low-Z
Output
Min
10
ns
t
BLZ
UB#, LB# Enable to Low-Z Output
Min
10
ns
t
OLZ
Output Enable to Low-Z Output
Min
5
ns
t
HZ1
, t
HZ2
Chip Disable to High-Z Output
Max
25
ns
t
BHZ
UB#s, LB#s Disable to High-Z Output
Max
25
ns
t
OHZ
Output Disable to High-Z Output
Max
25
ns
t
OH
Output Data Hold from Address Change
Min
10
ns
Address
Data Out
Previous Data Valid
Data Valid
t
AA
t
RC
t
OH
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| AM45DL3208GB70IS | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM |
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| AM45DL3208GB70IS | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM |
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| AM45DL3208GB85IT | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM |
| AM45DL3208GT70IS | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM |
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