參數(shù)資料
型號： AM41DL6408G70IS
廠商： SPANSION LLC
元件分類： 存儲器
英文描述： Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
中文描述： SPECIALTY MEMORY CIRCUIT, PBGA73
封裝： 8 X 11.60 MM, FBGA-73
文件頁數(shù)： 9/63頁
文件大?。?/td> 1139K
代理商： AM41DL6408G70IS
8
Am41DL6408G
August 19, 2002
P R E L I M I N A R Y
PIN DESCRIPTION
A18–A0
= 19 Address Inputs (Common)
A21–A19, A-1 = 4 Address Inputs (Flash)
SA
= Highest Order Address Pin (SRAM)
Byte mode
DQ15–DQ0
= 16 Data Inputs/Outputs (Common)
CE#f
= Chip Enable (Flash)
CE#s
= Chip Enable (SRAM)
OE#
= Output Enable (Common)
WE#
= Write Enable (Common)
RY/BY#
= Ready/Busy Output
UB#s
= Upper Byte Control (SRAM)
LB#s
= Lower Byte Control (SRAM)
CIOf
= I/O Configuration (Flash)
CIOf = V
IH
= Word mode (x16),
CIOf = V
IL
= Byte mode (x8)
= I/O Configuration (SRAM)
CIOs = V
IH
= Word mode (x16),
CIOs = V
IL
= Byte mode (x8)
= Hardware Reset Pin, Active Low
CIOs
RESET#
WP#/ACC
= Hardware Write Protect/
Acceleration Pin (Flash)
V
CC
f
= Flash 3.0 volt-only single power sup-
ply (see Product Selector Guide for
speed options and voltage supply
tolerances)
V
CC
s
V
SS
NC
= SRAM Power Supply
= Device Ground (Common)
= Pin Not Connected Internally
LOGIC SYMBOL
19
16 or 8
DQ15–DQ0
A18–A0
CE#f
OE#
WE#
RESET#
UB#s
RY/BY#
WP#/ACC
SA
A21–A19, A-1
LB#s
CIOf
CIOs
CE1#s
CE2s
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