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參數(shù)資料
| 型號： | AM29LV2562M |
| 廠商： | Spansion Inc. |
| 英文描述： | 512 Megabit (16 M x 32-Bit/32 M x 16-Bit) MirrorBit 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/O Control |
| 中文描述： | 512兆位（16 M中的x 32-Bit/32 M中的x 16位）的MirrorBit 3.0伏特，只有統(tǒng)一閃存部門與VersatileI / O控制 |
| 文件頁數(shù)： | 48/69頁 |
| 文件大?。?/td> | 1451K |
| 代理商： | AM29LV2562M |
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46
Am29LV2562M
October 9, 2003
P R E L I M I N A R Y
The remaining scenario is that the system initially de-
termines that the toggle bit is toggling and DQ5 and/or
DQ13 has not gone high. The system may continue to
monitor the toggle bits and DQ5 and DQ13 through
successive read cycles, determining the status as de-
scribed in the previous paragraph. Alternatively, it may
choose to perform other system tasks. In this case, the
system must start at the beginning of the algorithm
when it returns to determine the status of the opera-
tion (top of Figure 8).
DQ5 and DQ13: Exceeded Timing Limits
DQ5 indicates whether the program, erase, or
write-to-buffer time has exceeded a specified internal
pulse count limit. Under these conditions DQ5 and DQ13
produce a “1,” indicating that the program or erase cycle
was not successfully completed.
The device may output a “1” on DQ5 and/or DQ13 if
the system tries to program a “1” to a location that was
previously programmed to “0.”
Only an erase opera-
tion can change a “0” back to a “1.”
Under this con-
dition, the device halts the operation, and when the
timing limit has been exceeded, DQ5 and/or DQ13
produces a “1.”
In all these cases, the system must write the reset
command to return the device to the reading the array
(or to erase-suspend-read if the device was previously
in the erase-suspend-program mode).
DQ3 and DQ11: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 and DQ11 to determine
whether or not erasure has begun. (The sector erase
timer does not apply to the chip erase command.) If
additional sectors are selected for erasure, the entire
time-out also applies after each additional sector
erase command. When the time-out period is com-
plete, DQ3 and DQ11 switch from a “0” to a “1.” If the
time between additional sector erase commands from
the system can be assumed to be less than 50 μs, the
system need not monitor DQ3 and DQ11. See also the
Sector Erase Command Sequence section.
After the sector erase command is written, the system
should read the status of DQ7 and DQ15 (Data# Poll-
ing) or DQ6 and DQ14 (Toggle Bits I) to ensure that
the device has accepted the command sequence, and
then read DQ3 and DQ11. If DQ3 and DQ11 are “1,”
the Embedded Erase algorithm has begun; all further
commands (except Erase Suspend) are ignored until
the erase operation is complete. If DQ3 and DQ11 are
“0,” the device will accept additional sector erase com-
mands. To ensure the command has been accepted,
the system software should check the status of DQ3
and DQ11 prior to and following each subsequent sec-
tor erase command. If DQ3 and DQ11 are high on the
second status check, the last command might not
have been accepted.
Table 12 shows the status of DQ3 and DQ11 relative
to the other status bits.
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