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| 型號(hào)： | AM29BDS640GTC9WSI |
| 廠商： | SPANSION LLC |
| 元件分類： | DRAM |
| 英文描述： | 64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory |
| 中文描述： | 4M X 16 FLASH 1.8V PROM, 20 ns, PBGA80 |
| 封裝： | 11 X 12 MM, 0.80 MM PITCH, FBGA-80 |
| 文件頁(yè)數(shù)： | 42/65頁(yè) |
| 文件大小： | 899K |
| 代理商： | AM29BDS640GTC9WSI |
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October 31, 2002
Am29BDS640G
41
A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
Notes:
1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two
cycles to seven cycles. Clock is set for active rising edge.
2. If any burst address occurs at a 64-word boundary, one additional clock cycle is inserted, and is indicated by RDY.
3. The device is in synchronous mode.
4. A17 = 1.
Figure 13.
Synchronous Burst Mode Read
Note:
Figure assumes 7 wait states for initial access, 54 MHz clock, and automatic detect synchronous read. D0–D7 in data
waveform indicate the order of data within a given 8-word address range, from lowest to highest. Data will wrap around within
the 8 words non-stop unless the RESET# is asserted low, or AVD# latches in another address. Starting address in figure is the
7th address in range (A6). See “Requirements for Synchronous (Burst) Read Operation”. The Set Configuration Register
command sequence has been written with A18=1; device will output RDY with valid data.
Figure 14.
8-word Linear Burst with Wrap Around
Da
Da + 1
Da + n
OE#
DQ15
-
DQ0
A21
-
A0
Aa
AVD#
RDY
CLK
CE#
t
CAS
t
AAS
t
AVC
t
AVD
t
AAH
t
OE
t
RACC
t
OEZ
t
CEZ
t
IACC
t
BDH
7 cycles for initial access shown.
Hi-Z
Hi-Z
Hi-Z
1
2
3
4
5
6
7
t
RDYS
t
BACC
t
ACC
D6
D7
OE#
DQ15
-
DQ0
A21
-
A0
Aa
AVD#
RDY
CLK
CE#
t
CES
t
ACS
t
AVDS
t
AVD
t
ACH
t
OE
t
IACC
t
ACC
t
BDH
D0
D1
D5
D6
7 cycles for initial access shown.
18.5 ns typ. (54 MHz)
Hi-Z
t
RACC
1
2
3
4
5
6
7
t
RDYS
t
BACC
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