參數(shù)資料
型號： AM29BDS640GTC9WSI
廠商： SPANSION LLC
元件分類： DRAM
英文描述： 64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
中文描述： 4M X 16 FLASH 1.8V PROM, 20 ns, PBGA80
封裝： 11 X 12 MM, 0.80 MM PITCH, FBGA-80
文件頁數(shù)： 12/65頁
文件大小： 899K
代理商： AM29BDS640GTC9WSI
October 31, 2002
Am29BDS640G
11
A D V A N C E I N F O R M A T I O N
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself
does not occupy any addressable memory location.
The register is composed of latches that store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the
inputs and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Table 1.
Device Bus Operations
Legend:
L = Logic 0, H = Logic 1, X = Don’t Care, S = Stable Logic 0 or 1 but no transitions.
Note:
Default active edge of CLK is the rising edge.
Enhanced VersatileIO (V
IO
) Control
The Enhanced VersatileIO (V
IO
) control allows the host
system to set the voltage levels that the device gener-
ates at its data outputs and the voltages tolerated at its
data and address inputs to the same voltage level that
is asserted on the V
IO
pin. The device is available with
either 1.65–1.95 or 2.7–3.15 V
IO
. This allows the
device to operate in 1.8 V or 3 V system environments
as required.
For example, a V
IO
of 2.7 – 3.15 volts allows for I/O at
the 3 volt level, driving and receiving signals to and
from other 3 V devices on the same bus.
Requirements for Asynchronous Read
Operation (Non-Burst)
To read data from the memory array, the system must
first assert a valid address on A21–A0, while driving
AVD# and CE# to V
IL
. WE# should remain at V
IH
. The
rising edge of AVD# latches the address. The data will
appear on DQ15–DQ0. Since the memory array is
divided into four banks, each bank remains enabled for
read access until the command register contents are
altered.
Address access time (t
ACC
) is equal to the delay from
stable addresses to valid output data. The chip enable
access time (t
CE
) is the delay from the stable
addresses and stable CE# to valid data at the outputs.
The output enable access time (t
OE
) is the delay from
the falling edge of OE# to valid data at the output.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition.
Operation
CE#
OE#
WE#
A21–0
DQ15–0
RESET#
CLK
(See
Note)
AVD#
Asynchronous Read - Addresses Latched
L
L
H
Addr In
I/O
H
X
Asynchronous Read - Addresses Steady State
L
L
H
Addr In
I/O
H
X
L
Asynchronous Write
L
H
L
Addr In
I/O
H
L
L
Synchronous Write
L
H
L
Addr In
I/O
H
Standby (CE#)
H
X
X
HIGH Z
HIGH Z
H
X
X
Hardware Reset
X
X
X
HIGH Z
HIGH Z
L
X
X
Burst Read Operations
Load Starting Burst Address
L
X
H
Addr In
X
H
Advance Burst to next address with appropriate
Data presented on the Data Bus
L
L
H
HIGH Z
Burst
Data Out
H
H
Terminate current Burst read cycle
H
X
H
HIGH Z
HIGH Z
H
X
Terminate current Burst read cycle via RESET#
X
X
H
HIGH Z
HIGH Z
L
X
X
Terminate current Burst read cycle and start
new Burst read cycle
L
X
H
HIGH Z
I/O
H
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