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參數(shù)資料
| 型號： | AM29BDS640GTC9WSI |
| 廠商： | SPANSION LLC |
| 元件分類： | DRAM |
| 英文描述： | 64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory |
| 中文描述： | 4M X 16 FLASH 1.8V PROM, 20 ns, PBGA80 |
| 封裝： | 11 X 12 MM, 0.80 MM PITCH, FBGA-80 |
| 文件頁數(shù)： | 10/65頁 |
| 文件大?。?/td> | 899K |
| 代理商： | AM29BDS640GTC9WSI |
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October 31, 2002
Am29BDS640G
9
A D V A N C E I N F O R M A T I O N
INPUT/OUTPUT DESCRIPTIONS
A21-A0
=
Address inputs
DQ15-DQ0 =
Data input/output
CE#
=
Chip Enable input. Asynchronous
relative to CLK for the Burst mode.
OE#
=
Output Enable input. Asynchronous
relative to CLK for the Burst mode.
WE#
=
Write Enable input.
V
CC
=
Device Power Supply
(1.65 – 1.95 V).
V
IO
=
Input & Output Buffer Power Supply
(either 1.65 – 1.95 V or 2.7 – 3.15 V).
V
SS
V
SSIO
NC
=
Ground
=
Output Buffer Ground
=
No Connect; not connected internally
RDY
=
Ready output; indicates the status of
the Burst read. Low = data not valid at
expected time. High = data valid.
CLK
=
CLK is not required in asynchronous
mode. In burst mode, after the initial
word is output, subsequent active
edges of CLK increment the internal
address counter.
AVD#
=
Address Valid input. Indicates to
device that the valid address is
present on the address inputs
(A21–A0).
Low = for asynchronous mode,
indicates valid address; for burst
mode, causes starting address to be
latched.
High = device ignores address inputs
RESET#
=
Hardware reset input. Low = device
resets and returns to reading array
data
WP#
=
Hardware write protect input. At V
IL
,
disables program and erase functions
in the two outermost sectors. Should
be at V
IH
for all other conditions.
At V
ID
, accelerates programming;
automatically places device in unlock
bypass mode. At V
IL
, locks all sectors.
Should be at V
IH
for all other
conditions.
ACC
=
LOGIC SYMBOL
22
16
DQ15–DQ0
A21–A0
CE#
OE#
WE#
RESET#
CLK
RDY
AVD#
WP#
ACC
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