參數(shù)資料
型號: AK5701KN
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: 16-Bit ツヒ Stereo ADC with PLL & MIC-AMP
中文描述: 16位ツヒ立體聲ADC帶鎖相環(huán)
文件頁數(shù): 54/64頁
文件大?。?/td> 747K
代理商: AK5701KN
[AK5701]
5.
EXT Master Mode
TE3-0 bits
(Addr:1DH, D7-4)
"0101"
(1)
Power Supply
PDN pin
PMVCM bit
(Addr:10H, D2)
(2)
(3)
MCKI pin
Input
M/S bit
(Addr:11H, D1)
BCLK pin
LRCK pin
Output
TMASTER bit
(Addr:1EH, D1)
"1010"
Example:
Audio I/F Format: I2S
BCLK frequency at Master Mode: 64fs
Input Master Clock Select: 256fs
Sampling Frequency: 44.1kHz
(1) Power Supply & PDN pin = “L”
“H”
(3)Addr:10H, Data:04H
(2)Addr:11H, Data:26H
Addr:14H, Data:23H
Addr:15H, Data:2FH
Addr:1DH, Data:50H
Addr:1EH, Data:02H
BCLK and LRCK output
Figure 49. Clock Set Up Sequence (5)
<Example>
(1) After Power Up: PDN pin “L”
“H”
“L” time of 150ns or more is needed to reset the AK5701.
(2) DIF1-0, FS1-0, BCKO1-0, M/S, TE3-0 and TMASTER bits should be set during this period as follows.
(2a) M/S bit = “1”, setting of FS3-0 and BCKO1-0 bits.
(2b) Setting of DIF1-0 bits.
(2c) TE3-0 bits = “0101”
(2d) TMASTER bit = “1”: BCLK and LRCK start to output.
(3) Power Up VCOM: PMVCM bit = “0”
“1”
VCOM should first be powered up before the other block operates.
When the clock mode is changed from EXT Master Mode to other modes, the register should be set as
Table 1
after PDN
pin = “L” to “H” or TE3-0 bits = “1010”.
MS0404-E-02
2007/08
- 54 -
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