參數(shù)資料
型號(hào)： AK5701KN
廠商： Asahi Kasei Microsystems Co.,Ltd
英文描述： 16-Bit ツヒ Stereo ADC with PLL & MIC-AMP
中文描述： 16位ツヒ立體聲ADC帶鎖相環(huán)
文件頁(yè)數(shù)： 39/64頁(yè)
文件大小： 747K
代理商： AK5701KN
[AK5701]
When writing to the IVL7-0 and IVR7-0 bits continuouslly, the control register should be written in an interval more than
zero crossing timeout. If not, IVL and IVR are not changed since zero crossing counter is reset at every write operation. If
the same register value as the previous write operation is written to IVL and IVR, this write operation is ignored and zero
crossing counter is not reset. Therefore, IVL and IVR can be written in an interval less than zero crossing timeout.
ALC bit
ALC Status
Disable
Enable
Disable
IVL7-0 bits
E1H(+30dB)
IVR7-0 bits
C6H(+20dB)
Internal IVL
E1H(+30dB)
E1(+30dB) --> F1(+36dB)
E1(+30dB)
Internal IVR
C6H(+20dB)
E1(+30dB) --> F1(+36dB)
C6H(+20dB)
(1)
(2)
Figure 40. IVOL value during ALC operation
(1)
The IVL value becomes the start value if the IVL and IVR are different when the ALC starts. The wait time from
ALC bit = “1” to ALC operation start by IVL7-0 bits is at most recovery time (WTM1-0 bits) plus zerocross timeout
period (ZTM1-0 bits).
(2)
Writing to IVL and IVR registers (18H and 19H) is ignored during ALC operation. After ALC is disabled, the IVOL
changes to the last written data by zero crossing or timeout. When ALC is enabled again, ALC bit should be set to “1”
by an interval more than zero crossing timeout period after ALC bit = “0”.
■
System Reset
When power-up, the AK5701 should be reset by bringing the PDN pin = “L”. This ensures that all internal registers reset
to their initial values.
The ADC enters an initialization cycle that starts when the PMADL or PMADR bit is changed from “0” to “1”. The
initialization cycle time is 3088/fs=70.0ms@fs=44.1kHz when HPF1-0 bits are “00” (
Table 30
). During the initialization
cycle, the ADC digital data outputs of both channels are forced to a 2’s compliment, “0”. The ADC output reflects the
analog input signal after the initialization cycle is complete.
Init Cycle
(default
)
HPF1 bit
HPF0 bit
Cycle
fs=44.1kHz
70.0ms
(Recommendation)
fs=22.05kHz
fs=11.025kHz
0
0
3088/fs
140.0ms
280.1ms
0
1
1552/fs
35.2ms
70.4ms
140.8ms
(Recommendation)
1
0
784/fs
17.8ms
35.6ms
71.1ms
(Recommendation)
N/A
1
1
N/A
N/A
N/A
Table 30. ADC Initialization Cycle (N/A: Not available)
MS0404-E-02
2007/08
- 39 -
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