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參數(shù)資料
| 型號(hào)： | AK5701KN |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | 16-Bit ツヒ Stereo ADC with PLL & MIC-AMP |
| 中文描述： | 16位ツヒ立體聲ADC帶鎖相環(huán) |
| 文件頁(yè)數(shù)： | 29/64頁(yè) |
| 文件大?。?/td> | 747K |
| 代理商： | AK5701KN |
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[AK5701]
■
Audio Interface Format
Fore types of data format are available and are selected by setting the DIF1-0 bits (
Table 15
). In all modes, the serial data
is MSB first, 2’s complement format. Audio interface formats can be used in both master and slave modes, but DSP Mode
1 supports PLL Master Mode only. LRCK, BCLK and SDTO pins are used in master mode. EXLRCK, EXBCLK and
SDTO pins are used in slave mode. In modes 2 and 3, the SDTO is clocked out on the falling edge (“
↓
”) of
BCLK/EXBCLK.
Mode
DIF1 bit
DIF0 bit
SDTO
0
0
0
DSP Mode 0
1
0
1
DSP Mode 1
2
1
0
MSB justified
I
2
S compatible
3
1
1
Table 15. Audio Interface Format
In Modes 0 and 1 (DSP mode 0 and 1), the audio I/F timing is changed by BCKP and MSBS bits.
When BCKP bit is “0”, SDTO data is output by rising edge (“
↑
”) of BCLK/EXBCLK.
When BCKP bit is “1”, SDTO data is output by falling edge (“
↓
”) of BCLK/EXBCLK.
MSB data position of SDTO can be shifted by MSBS bit. The shifted period is a half of BCLK/EXBCLK.
DIF1
DIF0
MSBS
BCKP
MSB of SDTO is output by the rising edge (“
↑
”) of the first
BCLK/EXBCLK after the rising edge (“
↑
”) of LRCK/EXLRCK (
Figure
26
).
MSB of SDTO is output by the falling edge (“
↓
”) of the first
BCLK/EXBCLK after the rising edge (“
↑
”) of LRCK/EXLRCK (
Figure
27
).
MSB of SDTO is output by next rising edge (“
↑
”) of the falling edge (“
↓
”)
of the first BCLK/EXBCLK after the rising edge (“
↑
”) of LRCK/EXLRCK
(
Figure 28
).
MSB of SDTO is output by next falling edge (“
↓
”) of the rising edge (“
↑
”)
of the first BCLK/EXBCLK after the rising edge (“
↑
”) of LRCK/EXLRCK
(
Figure 29
).
MSB of SDTO is output by the rising edge (“
↑
”) of the first
BCLK/EXBCLK after the rising edge (“
↑
”) of LRCK/EXLRCK (
Figure
30
).
MSB of SDTO is output by the falling edge (“
↓
”) of the first
BCLK/EXBCLK after the rising edge (“
↑
”) of LRCK/EXLRCK (
Figure
31
).
MSB of SDTO is output by next rising edge (“
↑
”) of the falling edge (“
↓
”)
of the first BCLK/EXBCLK after the rising edge (“
↑
”) of LRCK/EXLRCK
(
Figure 32
).
MSB of SDTO is output by next falling edge (“
↓
”) of the rising edge (“
↑
”)
of the first BCLK/EXBCLK after the rising edge (“
↑
”) of LRCK/EXLRCK
(
Figure 33
).
Table 16. Audio Interface Format in Mode 0, 1
If 16-bit data that ADC outputs is converted to 8-bit data by removing LSB 8-bit, “
1” at 16bit data is converted to “
1”
at 8-bit data. And when the DAC playbacks this 8-bit data, “
1” at 8-bit data will be converted to “
256” at 16-bit data
and this is a large offset. This offset can be removed by adding the offset of “128” to 16-bit data before converting to 8-bit
data.
BCLK, EXBCLK
32fs
≥
32fs
≥
32fs
≥
32fs
Figure
(default)
See
Table 16
Figure 34
Figure 35
Audio Interface Format
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
1
1
1
(default)
MS0404-E-02
2007/08
- 29 -
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AK5701_07 | 16-Bit ツヒ Stereo ADC with PLL & MIC-AMP |
| AK5701VN | 16-Bit ツヒ Stereo ADC with PLL & MIC-AMP |
| AK5701 | digital audio 16bit A/D converter |
| AK5702 | 4-Channel ADC with PLL & MIC-AMP |
| AK5702VN | 4-Channel ADC with PLL & MIC-AMP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AK5701KNP-L | 制造商:AKM Semiconductor Inc 功能描述:AK5701KNP-L |
| AK5701VN | 制造商:AKM 制造商全稱:AKM 功能描述:PLL & MIC-AMP 16-Bit Stereo ADC |
| AK5701VNP-L | 功能描述:IC ADC AUDIO STER 16BIT 24QFN RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - ADCs/DAC - 專用型 系列:- 產(chǎn)品培訓(xùn)模塊:Data Converter Basics 標(biāo)準(zhǔn)包裝:1 系列:- 類型:電機(jī)控制 分辨率（位）:12 b 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，并聯(lián) 電壓電源:單電源 電源電壓:2.7 V ~ 3.6 V，4.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:100-TQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:剪切帶 (CT) 其它名稱:296-18373-1 |
| AK5702 | 制造商:AKM 制造商全稱:AKM 功能描述:portable digital audio 16bit A/D converter |
| AK5702VN | 制造商:AKM 制造商全稱:AKM 功能描述:4-Channel ADC with PLL & MIC-AMP |
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