參數(shù)資料
型號: AK5701KN
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: 16-Bit ツヒ Stereo ADC with PLL & MIC-AMP
中文描述: 16位ツヒ立體聲ADC帶鎖相環(huán)
文件頁數(shù): 43/64頁
文件大小: 747K
代理商: AK5701KN
[AK5701]
Addr
12H
Register Name
Signal Select
Default
D7
0
0
D6
0
0
D5
0
0
D4
D3
D2
D1
INR
0
D0
INL
0
PMMP
0
MDIF2
0
MDIF1
0
INL: ADC Lch Input Source Select
0: LIN1 pin (default)
1: LIN2 pin
INR: ADC Rch Input Source Select
0: RIN1 pin (default)
1: RIN2 pin
MDIF1: ADC Lch Input Type Select
0: Single-ended input (LIN1/LIN2 pin: default)
1: Full-differential input (LIN+/LIN
pin)
MDIF2: ADC Rch Input Type Select
0: Single-ended input (RIN1/RIN2 pin: default)
1: Full-differential input (RIN+/RIN
pin)
PMMP: MPWR pin Power Management
0: Power down: Hi-Z (default)
1: Power up
Addr
Register Name
13H
Mic Gain Control
Default
MGAIN1-0: MIC-Amp Gain Control (
Default: “01”(+15dB)
Addr
Register Name
14H
Audio Format Select
Default
DIF1-0: Audio Interface Format (
Default: “11” (I
2
S)
BCKP: BCLK/EXBCLK Polarity at DSP Mode (
Table 16
)
“0”: SDTO is output by the rising edge (“
”) of BCLK/EXBCLK. (default)
“1”: SDTO is output by the falling edge (“
”) of BCLK/EXBCLK.
MSBS: LRCK/EXLRCK Polarity at DSP Mode (
Table 16
)
“0”: The rising edge (“
”) of LRCK/EXLRCK is half clock of BCLK/EXBCLK before the channel change.
(default)
“1”: The rising edge (“
”) of LRCK/EXLRCK is one clock of BCLK/EXBCLK before the channel change.
MIX: ADC Output Data Select (
Table 17
)
“0”: Normal operation (default)
“1”: (L+R)/2
D7
0
0
D6
0
0
D5
0
0
D4
0
0
D3
0
0
D2
0
0
D1
D0
MGAIN1
0
MGAIN0
1
Table 20
)
D7
0
0
D6
0
0
D5
1
1
D4
MIX
0
D3
MSBS
0
D2
BCKP
0
D1
DIF1
1
D0
DIF0
1
Table 15
)
MS0404-E-02
2007/08
- 43 -
相關(guān)PDF資料
PDF描述
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